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80HCPS1848CBRI

Description
Switch ICs - Various S-RIO GEN 2
CategoryWireless rf/communication    Telecom circuit   
File Size1MB,86 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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80HCPS1848CBRI Overview

Switch ICs - Various S-RIO GEN 2

80HCPS1848CBRI Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeFCBGA
package instructionFCBGA-784
Contacts784
Manufacturer packaging codeBR784H1
Reach Compliance Codenot_compliant
ECCN codeEAR99
Samacsys DescriptionNULL
JESD-30 codeS-PBGA-B784
JESD-609 codee1
length29 mm
Humidity sensitivity level4
Number of functions1
Number of terminals784
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA784,28X28,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)245
power supply1,2.5/3.3 V
Certification statusNot Qualified
Maximum seat height3.44 mm
Maximum slew rate7940 mA
Nominal supply voltage1 V
surface mountYES
Telecom integrated circuit typesTELECOM CIRCUIT
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width29 mm
18-Port, 48-Lane, 240Gbps,
Gen2 RapidIO Switch
CPS-1848
Datasheet
Description
The CPS-1848 (80HCPS1848) is a
RapidIO Specification (Rev. 2.1)
compliant Central Packet Switch whose functionality is central to
routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other RapidIO-based devices. It can also be
used in RapidIO backplane switching. The CPS-1848 supports Serial
RapidIO (S-RIO) packet switching (unicast, multicast, and an optional
broadcast) from any of its 18 input ports to any of its 18 output ports.
Features
• RapidIO ports
48
bidirectional S-RIO lanes
— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
— Support Level I defined short or long haul reach, and Level II
defined short-, medium-, or long-run reach for each PHY speed
— Error Management Extensions support
— Software-assisted error recovery, supporting hot swap
• I
2
C Interfaces
— Provides I
2
C port for maintenance and error reporting
— Master or Slave operation
— Master allows power-on configuration from external ROM
— Master mode configuration with external image compressing and
checksum
• Switch
240
Gbps peak throughput
— Non-blocking data flow architecture
— Configurable for Cut-Through or Store-and-Forward data flow
— Very low latency for all packet lengths and load conditions
— Internal queuing buffer and retransmit buffer
— Standard transmitter- or receiver-controlled flow control
— Global routing or Local Port routing capability
— Supports up to 40 simultaneous multicast masks, with broadcast
— Performance monitoring counters for performance and
diagnostics analysis. Per input port and output port counters
• SerDes
— Transmitter pre-emphasis and drive strength + receiver
equalization provides best possible signal integrity
— Embedded PRBS generation and detection with programmable
polynomials support Bit Error Rate testing
• Additional Information
— Packet Trace/Mirror. Each input port can copy all incoming
packets matching user-defined criteria to a “trace” output port.
— Packet Filter. Each input port can filter (drop) all incoming packets
matching user-defined criteria.
— Device configurable through any of S-RIO ports, I
2
C, or JTAG
— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
Lidded/Lidless
784-FCBGA Package:
29
29 mm,
1.0 mm ball
pitch
Block Diagram
Quadrant 0
Lanes 0-3, 16-19, 32-35
Ports 0, 4, 8, 12, 16
Quadrant 3
Lanes 12-15, 28-31, 44-47
Ports 3, 7, 11, 15
CPS-1848
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I
2
C Controller
Ports 1, 5, 9, 13, 17
Lanes 4-7, 20-23, 36-39
Quadrant 1
JTAG Controller
Ports 2, 6, 10, 14
Lanes 8-11, 24-27, 40-43
Quadrant 2
Typical Applications
High-performance computing
Wireless
Defense and aerospace
Video and imaging
©2017 Integrated Device Technology, Inc.
1
June 26, 2017

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Description Switch ICs - Various S-RIO GEN 2 Switch ICs - Various RapidIO Switch Switch ICs - Various 80HCPS1848C RapidIO Gen 2 Switch Switch ICs - Various 80HCPS1848C RapidIO Gen 2 Switch Switch ICs - Various 80HCPS1848C RapidIO Gen 2 Switch
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology -
Is it lead-free? Contains lead Contains lead Lead free Lead free -
Is it Rohs certified? conform to conform to conform to conform to -
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) -
Parts packaging code FCBGA FCBGA FCBGA FCBGA -
Contacts 784 784 784 784 -
Manufacturer packaging code BR784H1 RM784 BLG784 BLG784 -
Reach Compliance Code not_compliant not_compliant compliant compliant -
Samacsys Description NULL FLIP CHIP BGA 29 X 29 MM 1.0 MM PITCH FLIP CHIP BGA 29 X 29 MM 1.0 MM PITCH FLIP CHIP BGA 29 X 29 MM 1.0 MM PITCH -
JESD-609 code e1 e1 e1 e1 -
Humidity sensitivity level 4 4 4 4 -
Peak Reflow Temperature (Celsius) 245 250 245 245 -
Terminal surface Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) -
Maximum time at peak reflow temperature NOT SPECIFIED 30 NOT SPECIFIED NOT SPECIFIED -
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