Freescale Semiconductor, Inc.
Advance Information
MPC860TS/D
Rev. 0.1, 11/2001
MPC860 PowerQUICC™
Technical Summary
Advance Information
Freescale Semiconductor, Inc...
MPC860 PowerQUICC™ Technical Summary
The MPC860 Quad Integrated Communications Controller (PowerQUICC™) is a versatile
one-chip integrated microprocessor and peripheral combination that can be used in a variety
of controller applications. It particularly excels in both communications and networking
systems. Unless otherwise specified, the PowerQUICC unit is referred to as the MPC860 in
this manual.
The MPC860 is a PowerPC architecture-based derivative of Motorola’s MC68360 Quad
Integrated Communications Controller (QUICC™). The CPU on the MPC860 is a 32-bit
MPC8xx core implementation that incorporates memory management units (MMUs) and
instruction and data caches. The communications processor module (CPM) from the
MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I
2
C)
channel. Digital signal processing (DSP) functionality has been added to the CPM. The
memory controller has been enhanced, enabling the MPC860 to support any type of memory,
including high-performance memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also been integrated.
The purpose of this manual is to describe the operation of all the MPC860 functionality with
concentration on the I/O functions. Additional information can be found in
Programming
Environments Manual for the PowerPC Architecture.
1.1 Features
The following list summarizes the key MPC860 features:
•
•
Embedded MPC8xx core
Single issue, 32-bit version of the core (compatible with the PowerPC architecture
definition) with 32, 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without
conditional execution
— 4-Kbyte data cache and 4-Kbyte instruction cache
— Instruction and data caches are two-way, set-associative, physical address, least
recently used (LRU) replacement, lockable on-line granularity
— MMUs with 32 entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16
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Features
•
•
•
•
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•
•
virtual address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Complete static design
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory
devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer and time base
— Real-time clock (RTC)
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT
MODE
, and
RESTART TRANSMIT
)
•
•
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MPC860 PowerQUICC™ Technical Summary
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Features
•
•
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•
— Up to 384 buffer descriptors (BDs)
— Supports continuous mode transmission and reception on all serial channels
— Up to 5 Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
Four SCCs (serial communication controllers)
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation (Available only
on specially programmed devices)
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
•
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
•
One I
2
C (inter-integrated circuit) port
— Supports master and slave modes
— Multiple-master environment support
•
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, clocking
— Allows dynamic changes
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Features
— Can be internally connected to six serial channels (four SCCs and two SMCs)
•
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC860 or MC68360
•
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— 8 memory or I/O windows supported
•
Low power support
— Full on—All units fully powered
— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
— Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for
fast wake up
— Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer.
— Power down mode— All units powered down except PLL, RTC, PIT, time base and
decrementer
•
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports Conditions: =
≠
< >
— Each watchpoint can generate a break point internally
•
•
3.3 V operation with 5-V TTL compatibility
357-pin ball grid array (BGA) package
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MPC860 PowerQUICC™ Technical Summary
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Architecture Overview
Instruction
Bus
MPC8xx
Processor
Core
4K
Instruction Cache
Instruction MMU
32 Entry ITLB
Unified
Bus
System Interface Unit (SIU)
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
System Functions
Real-Time Clock
PCMCIA-A Interface
TA
Load/Store
Bus
4K
Data Cache
Data MMU
32 Entry DTLB
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Parallel I/O
4 Baud Rate
Generators
4
Timers
Interrupt
Controllers
5 K Dual-Port
RAM
1
Parallel Interface
Timers
Port
32-Bit RISC Controller
and Program
ROM
16
Virtual
Serial
and
2
Independent
DMA
Channels
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
Serial Interface and Time-Slot Assigner (TSA)
Serial Interface
Figure 1. MPC860 Block Diagram
1.2
Architecture Overview
The MPC860 integrates an embedded MPC8xx core with high-performance, low-power peripherals to
extend the Motorola Data Communications family of embedded processors even farther into high-end
communications and networking products.
The MPC860 is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). The MPC860 block
diagram is shown in Figure 1.
1.3
Embedded MPC8xx Core
The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC architecture.
It is a fully static design that has an integer unit (IU) and a load/store unit (LSU). It executes all integer and
load/store operations in hardware. The core supports integer operations on a 32-bit internal data path and
32-bit arithmetic hardware. The core interface to the internal and external buses is 32 bits. The core can
operate on 32-bit external operands with one bus cycle.
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