Datasheet
Resistive Type Touch Screen Controller ICs
BU21023GUL BU21023MUV
General Description
Unlike most resistive touch screen controllers, the
BU21023 4-wire resistive touch screen controller
enables dual-touch detection and gesture recognition.
These intelligent controllers expose a set of registers to
a HOST processor and are configured through software.
The controllers can detect single point coordinates, dual
coordinates, pinch, spread, rotate left and rotate right
gestures, enabling pan and zoom operations in
applications that previously had to rely exclusively on
capacitive touch technology. Resistive touch does not
require custom screen development which reduces
development cost, and results in faster time to market
across a family of products.
Packages
VCSP50L2
VQFN028V5050
W(Typ) x D(Typ) x H(Max)
2.60mm x 2.60mm x 0.55mm
5.00mm x 5.00mm x 1.00mm
VCSP50L2
VQFN028V5050
Features
Enables single touch, dual touch & gesture
recognition using standard 4-wire resistive touch
screens
Adjustable touch detection threshold allows fine
tuning of pressure sensitivity for an application
Enables measurement of single point touch
pressure
SPI- and 2-wire serial interface for interfacing to
HOST processor
Programmable interrupt polarity
10-bit ADC provides sufficient resolution for finger
or stylus inputs
Firmware for internal CPU may be downloaded
from HOST processor or from an EEPROM
Includes filtering options to eliminate false
coordinates
Built in support for intelligent calibration
Easy to swap X & Y coordinates or adapt to
different touch screen connections
Single 3V power supply
Available in small packages and temperature
ranges
Ideally suited for consumer
Applications
Products with an LCD can benefit from pan and
zoom operations.
Smart phones, Digital Cameras, Video Cameras,
GPS Receivers, Printers,
Copiers, automotive navigation screens, touch
kiosks
Tablet PCs , Notebook PCs, LCD displays (with
USB interface)
Key Specifications and Lineup
Parameter
Screen
Maximum Detection Point
Integrated Filter Process
Gesture Detection
Supplied Voltage Range(V)
Temperature Range(°C)
Host I/F
Package
○Product
structure：Silicon monolithic integrated circuit
.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
BU21023GUL
4-wire resistive
touch screen
2
Yes
Yes
2.7 to 3.6
-20 to +85
4-wire SPI
2-wire serial
VCSP50L2
BU21023MUV
4-wire resistive
touch screen
2
Yes
Yes
2.7 to 3.6
-20 to +85
4-wire SPI
2-wire serial
VQFN028V5050
○This
product has no designed protection against radioactive rays
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BU21023GUL BU21023MUV BU21024FV-M
Pin Configuration and Pin Description
【BU21023GUL】
T4
PVDD
DVDD
VDD
VSS
ECL
EDA
SCL_SCK
SDA_SI
INT
A
XP
AVDD
DVDD_EXT
CLK_EXT
E
YN
SEL_CSB
SO
T3
IFSEL
B
XN
YP
RSTB
T1
T2
D
XN
YP
RSTB
T1
T2
C
YN
SEL_CSB
SO
T3
IFSEL
C
XP
AVDD
DVDD_EXT
CLK_EXT
D
ECL
EDA
SCL_SCK
SDA_SI
INT
B
T4
PVDD
DVDD
VDD
VSS
E
A
1
2
3
4
5
1
2
3
4
5
TOP VIEW (BALL SIDE DOWN)
BOTTOM VIEW (BALL SIDE UP)
No.
D1
C1
C2
B1
A1
A2
B3
A3
B4
A4
A5
C3
B5
C4
C5
D4
D5
D3
E5
D2
E4
E3
E2
E1
1.
2.
3.
Pin Name
YN
XN
YP
XP
T4
PVDD
AVDD
DVDD
DVDD_EXT
VDD
VSS
RSTB
CLK_EXT
T1
T2
T3
IFSEL
SO
INT
SEL_CSB
SDA_SI
SCL_SCK
EDA
ECL
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I/O
I
-
-
I
I
I
I
I
I
O
O
I
I/O
I
I/O
O
Function
Screen interface
Screen interface
Screen interface
Screen interface
Test pin
Regulator output (for supply screen voltage)
Regulator output (for supply analog block)
Regulator output (for supply digital block) or supply digital voltage
Digital voltage enable (H=Hi-z , L=DVDD Enable)
Supply voltage
Ground
H/W reset
Supply external clock for debug
Test pin
Test pin
Test pin
Interface select pin (L=SPI, H=2-wire serial)
SPI
Serial data output
2-wire
-
Interrupt output
SPI
Chip select
2-wire Slave address select
SPI
Serial data input
2-wire Serial data in-out
SPI
Serial clock input
2-wire Serial clock input
EEPROM SDA
EEPROM SCL
Figure
E
E
E
E
E
-
-
-
E
-
-
E
A
A
A
A
A
F
C
C
C
C
C
C
4.
5.
6.
7.
8.
9.
Please use
1.0µF
capacitors between AVDD and DVDD to GND, and leave PVDD terminal open.
If DVDD_EXT=”H“, the DVDD pin can be connected to an external 1.8V power source.
Please pull up the ECL, EDA, and INT pins using 10k ohm resistors as shown in the application diagram at the end of this document.
ECL and EDA pins may be directly connected to GND if an external EEPROM is not being used. Please connect a
0.1µF
capacitor between T4 and GND.
T1, T2 & T3 pins should be connected to GND.
When using the 2 wire serial interface, please pull up the SCL_SCK, SDA_SI pins via 10k ohms and leave SO unconnected.
Please note that the values of resistors and capacitors mentioned here are only recommended values.
RSTB should be held low until supply voltage VDD has ramped up and has reached a stable level.
The polarity of INT pin is programmable via register 0x30.
Connect CLK_EXT to GND for normal use.
INT terminal is used as input pin in test mode.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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BU21023GUL BU21023MUV BU21024FV-M
Pin Configuration and Pin Description - continued
16 CLK_EXT
【BU21023MUV】
IFSEL
SO
T3
T2
T1
RSTB
NC
NC
NC
YN
XN
17
21
20
19
18
15
5
YP
6
1
2
3
INT
SEL_CSB
SDA_SI
SCL_SCK
EDA
ECL
NC
22
23
24
25
26
27
28
14
13
12
11
10
9
8
VSS
VDD
DVDD_EXT
DVDD
AVDD
PVDD
T4
NC
ECL
EDA
SCL_SCK
SDA_SI
SEL_CSB
INT
28
27
26
25
24
23
22
4
7
8
9
10
11
12
13
14
XP
T4
PVDD
AVDD
DVDD
DVDD_EXT
VDD
VSS
20
21
19
18
17
NC
NC
XN
NC
YN
YP
XP
SO
T3
16
CLK_EXT
IFSEL
TOP VIEW (LEAD SIDE DOWN)
BOTTOM VIEW (LEAD SIDE UP)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1.
2.
3.
Pin name
NC
NC
NC
YN
XN
YP
XP
T4
PVDD
AVDD
DVDD
DVDD_EXT
VDD
VSS
RSTB
CLK_EXT
T1
T2
T3
IFSEL
SO
INT
SEL_CSB
SDA_SI
SCL_SCK
EDA
ECL
NC
I/O
-
-
-
I/O
I/O
I/O
I/O
I/O
O
O
I/O
I
-
-
I
I
I
I
I
I
O
O
I
I/O
I
I/O
O
-
Function
-
-
-
Screen interface
Screen interface
Screen interface
Screen interface
Test pin
Regulator output (for supply screen voltage)
Regulator output (for supply analog block)
Regulator output (for supply digital block) or supply digital voltage
Digital voltage enable (H=Hi-Z , L=DVDD enable)
Supply voltage
Ground
H/W reset
Supply external clock for debug
Test pin
Test pin
Test pin
Interface select pin (L=SPI, H=2-wire serial)
SPI
Serial data output
2-wire
-
Interrupt output
SPI
Chip select
2-wire Slave address select
SPI
Serial data input
2-wire Serial data in-out
SPI
Serial clock input
2-wire Serial clock input
EEPROM SDA
EEPROM SCL
-
RSTB
T2
T1
15
2
1
3
4
5
6
7
Figure
-
-
-
E
E
E
E
E
-
-
-
E
-
-
E
A
A
A
A
A
F
C
C
C
C
C
C
-
4.
5.
6.
7.
8.
9.
10.
11.
Please use
1.0µF
capacitors between AVDD and DVDD to GND, and leave PVDD terminal open.
If DVDD_EXT=”H “, the DVDD pin can be connected to an external 1.8V power source.
Please pull up the ECL, EDA, and INT pins using 10k ohm resistors as shown in the application diagram at the end of this document.
ECL and EDA pins may be directly connected to GND if an external EEPROM is not being used. Please connect a
0.1µF
capacitor between
T4 and GND. T1, T2 & T3 pins should be connected to GND.
When using the 2 wire serial interface, please pull up the SCL_SCK, SDA_SI pins via 10k ohms and leave SO unconnected.
Please note that the values of resistors and capacitors mentioned here are only recommended values.
RSTB should be held low until supply voltage VDD has ramped up and has reached a stable level.
The polarity of INT pin is programmable via register 0x30.
Connect CLK_EXT to GND for normal use.
INT terminal is used as input pin in test mode.
Unconnected NC terminals.
Please connect thermal PAD (Exposed PAD) to GND.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/17
TSZ02201-0L5L0F300840-1-2
7.June.2016 Rev.004
BU21023GUL BU21023MUV BU21024FV-M
I/O equivalence circuit
PAD
PAD
Figure A
Figure B
PAD
PAD
Figure C
Figure D
PAD
CIN
PAD
Figure E
Figure F
Figure BU21023GUL / BU21023MUV I/O Equivalent Circuit
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/17
TSZ02201-0L5L0F300840-1-2
7.June.2016 Rev.004
BU21023GUL BU21023MUV BU21024FV-M
Block Diagram and Description of each Block
【BU21023GUL
/ BU21023MUV】
Work
memory
XP
XN
YP
YN
Panel
I/F
ADC
(10bit)
EEPROM
I/F
ECL
EDA
CPU
(8bit)
Program
memory
CLK_EXT
Osc
Clock
generator
register
Host
I/F
Regulator
SEL_CSB
SCL_SCK
SDA_SI
SO
INT
IFSEL
DVDD_EXT
DVDD
PVDD
AVDD
VDD
VSS
RSTB
T1
T2
T3
Screen I/F
ADC
OSC
Regulator
Clock Generator
CPU Core
Work Memory
Program Memory
EEPROM I/F
Host I/F
4-wire resistive touch screen interface
10-bit A/D converter
Internal 20MHz oscillator block with optional external clock input
Internal regulator provides 1.8V DVDD supply. DVDD can also be supplied from an
external source if DVDD_EXT pin is tied high.
System clock and timing generation (10MHz CPU clock)
For dual touch processing, programmability and HOST interface
Data memory for CPU
Program memory for CPU. Code can be downloaded by HOST processor or from an
external EEPROM
To connect to external EEPROM when downloading program memory from EEPROM.
Use of external EEPROM is optional.
4-wire SPI or 2-wire serial interface provides access to registers
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/17
T4
TSZ02201-0L5L0F300840-1-2
7.June.2016 Rev.004
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