STD7NK30Z, STF7NK30Z
STP7NK30Z
N-channel, 300 V, 0.80
Ω,
5 A TO-220, TO-220FP, DPAK
Zener-protected SuperMESH™ Power MOSFET
Features
Type
STF7NK30Z
STP7NK30Z
STD7NK30Z
■
■
■
■
■
V
DSS
300 V
300 V
300 V
R
DS(on)
max
< 0.9
Ω
< 0.9
Ω
< 0.9
Ω
I
D
5A
5A
5A
Pw
20 W
50 W
50 W
1
3
2
TO-220FP
100% avalanche tested
Extremely high dv/dt capability
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatability
Applications
■
Switching application
Description
bs
O
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage Power MOSFETs including revolutionary
MDmesh™ products
et
l
o
ro
P
e
uc
d
s)
t(
O
-
Figure 1.
s
b
te
le
o
ro
P
uc
d
3
TO-220
s)
t(
3
1
2
1
DPAK
Internal schematic diagram
Table 1.
Device summary
Marking
D7NK30Z
F7NK30Z
P7NK30Z
Package
DPAK
TO-220FP
TO-220
Packaging
Tape and reel
Tube
Tube
Order codes
STD7NK30Z
STF7NK30Z
STP7NK30Z
March 2009
Rev 5
1/15
www.st.com
15
Electrical ratings
STx7NK30Z
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D
I
D
I
DM (2)
P
TOT
Absolute maximum ratings
Value
Parameter
TO-220, DPAK
Drain-source voltage (V
GS
= 0)
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Derating factor
5
3.2
20
50
0.4
300
± 30
5
(1)
3.2
(1)
20
(1)
TO-220FP
V
V
Unit
V
ESD(G-S)
dv/dt
(3)
V
ISO
T
j
T
stg
Gate source ESD(HBM-C=100 pF,
R=1.5 kΩ)
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t=1 s;T
C
=25 °C)
Operating junction temperature
Storage temperature
1. Limited only by maximum temperature allowed
2. Pulse width limited by safe operating area
3. I
SD
≤
5.7 A, di/dt
≤
200 A/µs, VDD =80% V
(BR)DSS.
Table 3.
b
O
et
l
so
Symbol
ro
P
e
T
l
uc
d
s)
t(
O
-
so
b
t
le
P
e
2800
4.5
ro
du
20
ct
s)
(
A
A
W
W/°C
V
V/ns
A
0.16
2500
V
-55 to 150
V
Absolute maximum ratings
Value
Parameter
TO-220, DPAK
2.50
62.5
300
TO-220FP
6.25
V
V
A
Unit
Rthj-case Thermal resistance junction-case Max
Rthj-amb
Thermal resistance junction-ambient Max
Maximum lead temperature for soldering
purpose
Table 4.
Symbol
I
AR
E
AS
Absolute maximum ratings
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by T
j
max)
Single pulse avalanche energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
5
130
Unit
A
mJ
2/15
STx7NK30Z
Electrical characteristics
2
Electrical characteristics
(Tcase =25 °C unless otherwise specified)
Table 5.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On/off states
Parameter
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
= 0)
Gate-body leakage
current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
=1 mA, V
GS
= 0
V
DS
=max rating
V
DS
=max rating @125 °C
V
GS
= ± 20 V
V
DS
= V
GS
, I
D
= 50 µA
V
GS
= 10 V, I
D
= 2.5 A
3
3.75
Min.
300
1
50
±10
Typ.
Max.
Unit
V
µA
µA
µA
V
Table 6.
Symbol
g
fs (1)
C
iss
C
oss
C
rss
Dynamic
Parameter
Test conditions
Forward transconductance V
DS
=15 V
,
I
D
= 2.5 A
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
C
oss eq. (2)
capacitance
bs
O
et
l
o
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.
2. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS.
ro
P
e
Q
g
Q
gs
Q
gd
Total gate charge
Gate-source charge
Gate-drain charge
uc
d
s)
t(
O
-
V
DS
= 25 V, f = 1MHz,
V
GS
= 0
so
b
te
le
ro
P
Min.
du
0.80
Typ.
2.5
380
74
15
30
13
4.5
7.6
ct
4.5
s)
(
0.90
Ω
Max.
Unit
S
pF
pF
pF
V
GS
= 0, V
DS
= 0 to 240 V
V
DD
= 240 V, I
D
= 7 A,
V
GS
= 10 V
Figure 16
pF
nC
nC
nC
17
3/15
Electrical characteristics
STx7NK30Z
Table 7.
Symbol
t
d(on)
t
r
t
d(off)
t
f
t
r(Voff)
t
f
t
c
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Off-voltage rise time
Fall time
Cross-over time
Test conditions
V
DD
= 150 V, I
D
= 3.5 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
Figure 15
V
DD
= 240 V, I
D
= 7 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
Figure 15
Min.
Typ.
11
25
20
10
8.5
8.5
20
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
Table 8.
Symbol
I
SD
I
SDM
(1)
Source Drain Diode
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward On voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 5 A, V
GS
= 0
Test conditions
Min.
Typ.
V
SD (2)
t
rr
Q
rr
I
RRM
I
SD
= 7 A, di/dt = 100 A/µs
V
DD
= 40 V, T
j
= 150 °C
Figure 20
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.
Table 9.
Symbol
BV
GSO(1)
Gate-source Zener diode
bs
O
et
l
o
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components
ro
P
e
Gate-source breakdown
voltage
uc
d
Parameter
s)
t(
O
-
so
b
te
le
r
P
d
o
uc
Max.
5
20
1.6
s)
t(
Unit
A
A
V
ns
nC
A
154
716
9.3
Test conditions
Igs=± 1mA (open drain)
Min.
30
Typ.
Max.
Unit
V
4/15
STx7NK30Z
Electrical characteristics
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area for TO-220
Figure 3.
Thermal impedance for TO-220
Figure 4.
Safe operating area for TO-220FP
Figure 5.
Figure 6.
bs
O
et
l
o
Output characteristics
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
Thermal impedance for TO-220FP
ro
P
uc
d
s)
t(
Figure 7.
Transfer characteristics
5/15
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