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849S625BYILF

Description
Clock Synthesizer / Jitter Cleaner Crystal-to-LVPECL LVDS Clock Synth
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size375KB,24 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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849S625BYILF Overview

Clock Synthesizer / Jitter Cleaner Crystal-to-LVPECL LVDS Clock Synth

849S625BYILF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePTQFP
package instructionHTFQFP,
Contacts48
Manufacturer packaging codeDXG48P2
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionTQFP 7 X7 X 1.0- EXPOSED PAD
JESD-30 codeS-PQFP-G48
JESD-609 codee3
length7 mm
Humidity sensitivity level3
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency630 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeHTFQFP
Package shapeSQUARE
Package formFLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
Master clock/crystal nominal frequency25 MHz
Maximum seat height1.2 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
Crystal-to-LVPECL/LVDS
Clock Synthesizer
Data Sheet
849S625
General Description
The 849S625 is a high frequency clock generator. The 849S625
uses an external 25MHz crystal to synthesize 625MHz, 312.5MHz,
156.25MHz and 125MHz clocks. The 849S625 has excellent
cycle-to-cycle and RMS phase jitter performance.
The 849S625 operates at full 3.3V supply mode and is available in a
fully RoHS compliant 48-lead TQFP, E-Pad package.
Features
Ten selectable differential LVPECL or LVDS outputs
Output frequencies of 625MHz, 312.5MHz, 156.25MHz or
125MHz using a 25MHz crystal.
Crystal interface designed for a 25MHz, parallel resonant crystal
Cycle-to-cycle jitter: 25ps (maximum)
RMS phase jitter at 156.25MHz (1MHz - 20MHz):
0.375ps (typical), LVDS outputs
Output duty cycle: 53% (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Frequency Table for Bank A, B and C Outputs
Crystal Frequency (MHz)
25
25
25
25
M Feedback Divider
25
25
25
25
VCO Frequency (MHz)
625
625
625
625
Nx Output Divider
1
2
4
5
Output Frequency (MHz)
625
312.5
156.25
125
Pin Assignment
V
CC
REF_CLK
V
EE
BYPASS
MR
SEL_OUT
SELA0
SELA1
V
CCA
QA0
nQA0
V
CCO
XTAL_IN
XTAL_OUT
V
EE
SELC0
SELC1
OEA
V
CC
OEB
OEC
SELB0
SELB1
V
EE
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
ICS849S625I
QA1
nQA1
QA2
nQA2
V
CCO
V
EE
QA3
nQA3
QA4
nQA4
QA5
nQA5
QC1
nQC0
QC0
nc
V
CCO
nQB1
QB1
nQB0
QB0
V
CCO
nQC1
48 Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc
1
V
CCO
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