5U49319NLG8 datasheet, PDF - EEWORLD Datasheet

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5U49319NLG8: DescriptionClock Generators & Support Products Very Low PWR CLK Freescale MCU 1.5V; CategoryThe embedded processor and controller Microcontrollers and processors; File Size309KB，20 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5U49319NLG8 Overview

Clock Generators & Support Products Very Low PWR CLK Freescale MCU 1.5V

5U49319NLG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	VFQFPN-48
Contacts	48
Manufacturer packaging code	NLG48P1
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	VFQFP-N 7 X7 X .9MM
JESD-30 code	S-XQCC-N48
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	3
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	66.66 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	27 MHz
Maximum seat height	0.9 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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DATASHEET

VERY LOW POWER CLOCK FOR FREESCALE MCU’S

IDT5U49319

General Description

The IDT5U49319 is a very low power clock for Freescale

MCU’s. It uses a 1.5V core and Low-Power HCSL

(LP-HCSL) differential outputs for minimal power

consumption. The SATA and SRC outputs are PCIe Gen1/2

compatible.

Features/Benefits

•

Various outputs are configurable to run in power down;

•

supports Wake_On_LAN

FPGA clock frequency is selectable via SMBus; allows

low-power system standby

Strapping pin sources SRC outputs from either spreading

or non-spreading PLL; maximum system flexibility

FLEX clock is pin selectable to be FPGA clock or USB

PHY clock; maximum system flexibility

TEST pin tri-states all outputs; speeds up board test

External 25MHz crystal; supports tight ppm

OE# pins; support SRC power management

Low power differential clock outputs; reduced power and

board space

Differential outputs internally terminated to 100

differential impedance; reduced board space

Space-saving 7x7mm 48-pin VFQFPN with 0.5mm pad

pitch; reduced board space without the need for fine pitch

assembly techniques

Recommended Application

Clock Chip for Freescale P10xx & P20xx MCU’s

Output Features

•

4 - LP-HCSL SRC pairs w/integrated source terminations

1 - LP-HCSL SATA pair w/integrated source terminations

1 - 25MHz 2.5V/3.3V LVCMOS output

2 - 66.66MHz 3.3V LVCMOS outputs

1 - FPGA 33.33MHz 2.5V/3.3V LVCMOS output

1 - FLEX clock 2.5V/3.3V LVCMOS output

1 - 125M GTX clock 2.5V LVCMOS output

1 - 26MHz 2.5V/3.3V LVCMOS output

Key Specifications

•

SRC/SATA cycle-to-cycle jitter <85ps

•

SRC/SATA PCIe Gen1/2 compliant

Block Diagram

25M

vMODE0

PLL A

-0.5%

3V66(1:0)

FPGACLK

SRC(3:0)_LRS

SATA_LRS

GTX125M

PLL B

non-SS

PLL C

vMODE1

SDATA_3.3

SCLK_3.3

^CLKPWRGD_PD#_3.3

vSS_EN_1.5

^OE(A:B)#_3.3

vvTEST_SEL_1.5

vFS(1:0)_1.5

Control

Logic

FLEXCLK

26M

IDT®

VERY LOW POWER CLOCK FOR FREESCALE MCU’S

IDT5U49319

REV D 043014

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