IN24LC04 datasheet, PDF - EEWORLD Datasheet

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IN24LC04: Description4K/8K 2.5V CMOS Serial EEPROMs; File Size188KB，10 Pages; ManufacturerINTEGRAL; Websitehttp://www.integral.by/english.phtml

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IN24LC04 Overview

4K/8K 2.5V CMOS Serial EEPROMs

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TECHNICAL DATA

4K/8K 2.5V CMOS Serial EEPROMs

DESCRIPTION

IN24LC04B/08B

IN24LC04B/08B is a 4K-or 8K-bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x

8 bit memory with a two wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and

active currents of only 5µA and 1mA respectively. The IN24LC04B/08B also has a page-write capability for up to 16

bytes of data. The IN24LC04B/08B is available in the standard 8-pin DIP.

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10

µA

standby current typical at 5.5V

- 5

µA

standby current typical at 3.0V

• Organized as two or four blocks of 256 bytes (2x256x8) and

(4x256x8)

• Two wire serial interface bus, I

C compatible

• Schmitt trigger, filtered inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 ERASE/WRITE cycles guaranteed*

• Data retention > 200 years

• 8-pin DIP

• Temperature range -40 to +85

VCC

AO, A1, A2

+2.5V to 5.5V Power Supply

No Internal Connection

Name

Vss

SDA

SCL

PACKAGE

= -40 ... +85

°C

PINNING

Function

Ground

Serial Address/Data I/O

Serial Clock

Write Protect Input

Pin Connection

Vss

Vcc

SCL

SDA

IN24LC04B/08B

Figure 3. Bus timing Data

FUNCTIONAL DESCRIPTION

The IN24LC04B/08B supports a bidirectional two wire bus and data transmission protocol. A

device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver.

The bus has to be controlled by a master device which generates the serial clock (SCL), controls the

bus access, and generates the START and STOP conditions, while the IN24LC04B/08B works as

slave. Both, master and slave can operate as transmitter or receiver but the master device

determines which mode is activated.

BUS CHARACTERISTICS

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (see Figure 4).

Bus not Busy (A)

Both data and clock lines remain HIGH.

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START

condition. All commands must be preceded by a START condition.

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP

condition. All operations must be ended with a STOP condition.

Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock

pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of the data bytes transferred between the START and STOP conditions is determined by the

master device and is theoretically unlimited, although only the last sixteen will be stored when

doing a write operation. When an overwrite does occur it will replace data in a first in first out

fashion.

IN24LC04B/08B

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of

each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

Note:

The IN24LC04B/08B does not generate any acknowledge bits if an internal programming cycle is in

progress

The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse

in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an

end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked

out of the slave. In this case, the slave must leave the data line HIGH to enable the master to

generate the STOP condition.

Figure 4. Data Transfer Sequence on the serial bus

BUS CHARACTERISTICS

Device Addressing and Operation

A control byte is the first byte received following the start condition from the master device. The

control byte consists of a four bit control code, for the IN24LC04B/08B this is set as 1010 binary

for read and write operations. The next three bits of the control byte are the block select bits (B2,

B1, BO). B2 is a don't care for both the IN24LC04B and IN24LC08B; B1 is a don't care for the

IN24LC04B. They are used by the master device to select which of the two or four 256 word blocks

of memory are to be accessed. These bits are in effect the most significant bits of the word address.

The last bit of the control byte defines the operation to be performed. When set to one a read

operation is selected, when set to zero a write operation is selected. Following the start condition,

the IN24LC04B/08B monitors the SDA bus checking the device type identifier being transmitted,

upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on

the state of the R/W bit, the IN24LC04B/ 08B will select a read or write operation.

Operation

Read

Write

Control Code

1010

Block Select

Block Address

R/W

IN24LC04 Related Products

	IN24LC04	IN24LC04B	IN24LC08	IN24LC08B	IN24LC04BD	IN24LC04BN	IN24LC04D	IN24LC04N	IN24LC08BD	IN24LC08BN
Description	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs	4K/8K 2.5V CMOS Serial EEPROMs

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