74LVC16374ADG-T datasheet, PDF

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74LVC16374ADG-T: DescriptionFlip Flops 3.3V 16-BIT POS D-TYPE 3-S; Categorylogic logic; File Size733KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC16374ADG-T Overview

Flip Flops 3.3V 16-BIT POS D-TYPE 3-S

74LVC16374ADG-T Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP48,.3,20
Contacts	48
Reach Compliance Code	unknown
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	12.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
Maximum Frequency@Nom-Sup	100000000 Hz
MaximumI(ol)	0.024 A
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Prop。Delay @ Nom-Sup	7 ns
propagation delay (tpd)	6.4 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	6.1 mm
Base Number Matches	1

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74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Rev. 11 — 16 January 2013

Product data sheet

1. General description

The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring

separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state

outputs for bus-oriented applications. It consists of two sections of eight positive

edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for

each octal.

The flip-flops store the state of their individual D-inputs that meet the set-up and hold time

requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin

nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE

does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed 3.3 V and

5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused

inputs.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pinout architecture

Low inductance multiple supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH16374A only)

High-impedance outputs when V

= 0 V

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

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