3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch
DATASHEET
REVISION 2-2
September 2017
PCI EXPRESS GEN 2 PACKET SWITCH
PI7C9X2G304SL
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-434-1040
Internet:
http://www.diodes.com
Document Number DS39933 Rev 2-2
PI7C9X2G304SL
IMPORTANT NOTICE
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Diodes Incorporated products are specif ically not authorized for use as critical components in life support devic es or systems w ithout
the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain lif e and whose failure to perform when properly used in accordance with instructions for use provided
in the labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or
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Customers must fully indemnify Diodes Incorporated and its representatives against any damages aris ing out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
Document Number DS39933 Rev 2-2
PI7C9X2G304SL
www.diodes.com
Page 3 of 88
September 2017
© Diodes Incorporated
PI7C9X2G304SL
REVISION HISTORY
Date
06/09/10
10/21/10
07/12/11
11/23/11
07/25/12
Revision Number
0.1
0.2
0.3
0.4
1.0
Description
Preliminary Datasheet
Added Section 6 EEPROM Interface And System M anagement Bus
Added Section 7 Register Description
Added Industrial Temperature Support (Section 1 Features, Section 11.1 Absolute
M aximum Ratings, Section 13 Ordering Information)
Updated Section 1 Features (integrated reference clock)
Updated Section 3.1 PCI Express Interface Signals (Added REFCLKI_P, REFCLKI_N,
REFCLKO_P[2:0], REFCLKO_N[2:0], and IREF)
Updated Section 1 Features (OBFF and LTR support)
Updated Section 3 Pin Description (
RXPOLINV_DIS, PRSNT [3:1], TEST4, T EST5, and
CVDDR
)
Updated Section 6 EEPROM Interface And System M anagement Bus
Updated Section 7 Register Description
Updated Section 3 Pin Description (PWR_SAV, TCK, and TRST_L)
Added Section 11.4 AC Switching Characteristics of Clock Buffer
Updated Table 8-1 Clock Requirement
Updated Table 3.5 Power Pins
Updated Table 4.1 Pin List of 129-Pin LQFP
Updated Section 1 (512-byte maximum payload size support, No-blocking capability)
Updated Section 3.2 Port Configuration Signals
Updated Section 3.3 M iscellaneous Signals
Updated Section 4.1 Pin List of 129-Pin LQFP
Updated Section 5.1 Physical Layer Circuit
Updated Section 5.1.7 Drive De-Emphasis
Updated Section 7.2.75 Device Capabilities Register (M ax_Payload_Size Supported)
Updated Section 13 Ordering Information
Updated Table 11-2 DC Electrical Characteristics
Updated Section 7.2 Transparent M ode Configuration Registers
Updated Section 8 Clock Scheme
Updated Section 3.1 PCI Express Interface Signals
Updated Section 3.2 Port Configuration Signals
Updated Section 5.1 Physical Layer Circuit
Updated Section 6.1 EEPROM Interface
Updated Section 7.2 Transparent M ode Configuration Registers
Updated Section 8 Clock Scheme
Updated Table 9-1 Instruction Register Codes
Updated Table 9-2 JTAG Device ID Register
Updated Table 9-3 JTAG Boundary Scan Register Definition
Updated Table 11-2 DC Electrical Characteristics
Updated Table 11-1 Absolute M aximum Ratings
Updated Section 3.1 PIN Description
Updated the Table 11-1 Absolute M aximum Ratings
Updated the Table 11-2 DC Electrical Characteristics
Added Section 11
Power Sequence
Updated Section 4.1 PIN LIST of 129-PIN LQFP
Updated Section 1 Features
Updated Section 3.2 Port Configuration Signals
Updated Section 5.1 Physical Layer Circuit
Updated Section 6.1.4 M apping EEPROM Contents to Configuration Registers
Updated Section 7.2 Transparent M ode Configuration Registers
Updated Section 12.1 Absolute M aximum Ratings
Updated Table 12-2 DC Electrical Characteristics
Added Section 12.4 Operating Ambient Temperature
Added Section 12.5 Power Consumption
Revision numbering system changed to whole number
01/02/13
1.1
07/15/14
1.2
11/17/14
07/16/15
1.3
1.4
09/07/15
12/23/15
03/04/16
09/05/17
1.5
1.6
1.7
2-2
Document Number DS39933 Rev 2-2
PI7C9X2G304SL
www.diodes.com
Page 4 of 88
September 2017
© Diodes Incorporated
PI7C9X2G304SL
TABLE OF CONTENTS
1
2
3
FEATUR ES ....................................................................................................................................................................................... 10
GEN ERAL DES CRIPTION ......................................................................................................................................................... 11
PIN DES CRIPTION ....................................................................................................................................................................... 13
3.1
3.2
3.3
3.4
3.5
4
5
4.1
PCI EXPRESS INTERFACE SIGNA LS .................................................................................................................... 13
PORT CONFIGURATION SIGNA LS ........................................................................................................................14
MISCELLANEOUS SIGNA LS....................................................................................................................................14
JTA G BOUNDARY SCAN SIGNA LS .......................................................................................................................15
POW ER PINS ..................................................................................................................................................................16
PIN LIST
OF
129-PIN LQFP .........................................................................................................................................17
PIN ASSIGNMENTS ...................................................................................................................................................................... 17
FUNCTIONAL DES CRIPTION ................................................................................................................................................. 18
5.1
PHYSICA L LA YER CIRCUIT ....................................................................................................................................18
5.1.1
RECEIVER DETECTION .................................................................................................................................18
5.1.2
RECEIVER SIGNAL DETEC TION .................................................................................................................19
5.1.3
RECEIVER EQUALIZATION ..........................................................................................................................19
5.1.4
TRANSMITTER S WING ....................................................................................................................................19
5.1.5
DRIVE AMPLITUDE AN D DE-EMPHASIS SETTINGS ............................................................................19
5.1.6
DRIVE AMPLITUDE.........................................................................................................................................20
5.1.7
DRIVE DE-EMPHASIS .....................................................................................................................................21
5.1.8
TRANSMITTER ELECTRICAL IDLE LATENCY .........................................................................................21
5.2
DATA LINK LA YER (DLL) ........................................................................................................................................21
5.3
TRANSACTION LA YER RECEIVE BLOCK (TLP DECAPSULATION) ........................................................ 22
5.4
ROUTING ........................................................................................................................................................................22
5.5
TC/ VC MAPPING ..........................................................................................................................................................22
5.6
QUEUE .............................................................................................................................................................................22
5.6.1
PH .........................................................................................................................................................................23
5.6.2
PD .........................................................................................................................................................................23
5.6.3
NPHD ...................................................................................................................................................................23
5.6.4
CPLH ....................................................................................................................................................................23
5.6.5
CPLD ....................................................................................................................................................................23
5.7
TRANSACTION ORDERING .....................................................................................................................................23
5.8
PORT ARBITRATION ..................................................................................................................................................24
5.9
VC A RBITRATION .......................................................................................................................................................24
5.10 FLOW CONTROL ..........................................................................................................................................................24
5.11 TRANSATION LA YER TRANSMIT BLOCK (TLP ENCAPSULATION) ....................................................... 25
5.12 A
CCESS
C
ONT ROL
S
ERVICE
............................................................................................................................................25
6
EEPROM INTERFACE AND S YSTEM MANAGEMENT B US ...................................................................................... 26
6.1
EEPROM INTERFA CE .................................................................................................................................................26
6.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................................26
6.1.2
EEPROM MODE AT RESET ...........................................................................................................................26
6.1.3
EEPROM SPACE ADDRESS MAP.................................................................................................................26
6.1.4
MAPPIN G EEPROM CONTENTS TO C ONFIGURATION REGISTERS ...............................................28
6.2
SMB
US
INTERFA CE .....................................................................................................................................................36
7
REGISTER DES CRIPTION ........................................................................................................................................................ 37
7.1
7.2
REGISTER TYPES.........................................................................................................................................................37
TRANSPA RENT MODE CONFIGURATION REGISTERS ................................................................................ 37
Page 5 of 88
September 2017
© Diodes Incorporated
Document Number DS39933 Rev 2-2
PI7C9X2G304SL
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PI7C9X2G304SL
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.2.24
7.2.25
7.2.26
7.2.27
7.2.28
7.2.29
7.2.30
7.2.31
7.2.32
7.2.33
7.2.34
7.2.35
7.2.36
7.2.37
7.2.38
7.2.39
7.2.40
7.2.41
7.2.42
7.2.43
7.2.44
7.2.45
7.2.46
7.2.47
7.2.48
7.2.49
7.2.50
7.2.51
7.2.52
7.2.53
7.2.54
7.2.55
7.2.56
VENDOR ID REGISTER – OFFSET 00h ......................................................................................................39
DEVICE ID REGISTER – OFFSET 00h ........................................................................................................39
COMMAND REGISTER – OFFSET 04h .......................................................................................................39
PRIMARY STATUS REGISTER – OFFSET 04h...........................................................................................40
REVISION ID REGISTER – OFFSET 08h ....................................................................................................41
CLASS CODE REGISTER – OFFSET 08h ....................................................................................................41
CACHE LINE REGISTER – OFFSET 0Ch....................................................................................................41
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................................................41
HEADER TYPE REGISTER – OFFSET 0Ch ................................................................................................41
PRIMARY BUS NUMBER REGIS TER – OFFSET 18h...............................................................................41
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................41
SUBORDINATE BUS N UMBER REGISTER – OFFSET 18h....................................................................42
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ..................................................................42
I/O BASE ADDRESS REGISTER – OFFSET 1Ch .......................................................................................42
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ......................................................................................42
SECONDARY STATUS REGISTER – OFFSET 1Ch ...................................................................................42
MEMORY BASE ADDRESS REGISTER – OFFSET 20h............................................................................43
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ..........................................................................43
PREFETC HABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h..........................................43
PREFETC HABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ........................................43
PREFETC HABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ..........44
PREFETC HABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ........44
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .........................................................44
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................................44
CAPABILITY POIN TER REGISTER – OFFSET 34h ..................................................................................44
INTERRUPT LINE REGISTER – OFFSET 3Ch...........................................................................................45
INTERRUPT PIN REGISTER – OFFSET 3Ch .............................................................................................45
BRIDGE C ONTROL REGISTER – OFFSET 3Ch ........................................................................................45
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h ......................................................46
POWER MANAGEMENT DATA REGISTER – OFFSET 44h ...................................................................46
PPB SUPPORT EXTENSIONS – OFFSET 44h............................................................................................47
DATA REGISTER – OFFSET 44h...................................................................................................................47
MSI CAPABILITY REGISTER – OFFSET 4Ch (Downstream Port Only)...............................................47
MESSAGE CON TROL REGISTER – OFFSET 4Ch (Downstream Port Only).......................................47
MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) ........................................47
MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) .........................48
MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) ................................................48
VPD CAPABILITY REGISTER – OFFSET 5Ch (Upstream Port Only)...................................................48
VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) ................................................................48
VENDOR SPECIFIC CAPABILITY REGIS TER – OFFSET 64h ..............................................................48
XPIP CSR0 – OFFSET 68h (Test Purpose Only) .........................................................................................49
XPIP CSR1 – OFFSET 6Ch (Test Purpose Only) ........................................................................................49
REPLAY TIME-OUT C OUNTER – OFFSET 70h ........................................................................................49
ACKNOWLEDGE LATENCY TIMER – OFFSET 70h ................................................................................49
SWITCH OPERATION MODE – OFFSET 74h (Upstream Port) .............................................................50
SWITCH OPERATION MODE – OFFSET 74h (Downstream Port) ........................................................51
XPIP_CSR2 – OFFSET 78h .............................................................................................................................51
PHY PARAMETER 1 – OFFSET 78h .............................................................................................................51
PHY PARAMETER 2 – OFFSET 7Ch ............................................................................................................52
XPIP_CSR3 – OFFSET 80h .............................................................................................................................52
XPIP_CSR4 – OFFSET 84h .............................................................................................................................52
XPIP_CSR5 – OFFSET 88h .............................................................................................................................53
TL_CSR – OFFSET 8Ch ...................................................................................................................................53
PHY PARAMETER 3 – OFFSET 90h .............................................................................................................54
PHY PARAMETER 4 - OFFSET 94h..............................................................................................................54
OPERATION MODE –OFFSET 98h ..............................................................................................................54
Page 6 of 88
September 2017
© Diodes Incorporated
Document Number DS39933 Rev 2-2
PI7C9X2G304SL
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