NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel input signal (LVPECL, CML, HSTL,
LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance,
noise immunity of the system design, and transmission line media, this
device will receive, drive or translate data or clock signals up to
1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin plug in
compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to V
CC
−
50 mV. This feature is ideal for translating
differential or single−ended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
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MARKING
DIAGRAM*
10
1
Micro−10
M SUFFIX
CASE 846B
A
Y
W
G
855S
AYWG
G
1
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
Guaranteed Input Clock Frequency up to 1.0 GHz
Guaranteed Input Data Rate up to 1.5 Gb/s
490 ps Maximum Propagation Delay
1.0 ps Maximum RMS Jitter
180 ps Maximum Rise/Fall Times
Single Power Supply; V
CC
= 3.3 V
±10%
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
GND + 50 mV to V
CC
−
50 mV V
CMR
Range
This is a Pb−Free Device
D0
D0
Q0
Q0
D1
D1
Q1
Q1
Functional Block Diagram
VOLTAGE (50 mV/div)
ORDERING INFORMATION
Device DDJ = 7 ps
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(V
INPP
= 100 mV, Input Signal DDJ = 24 ps)
©
Semiconductor Components Industries, LLC, 2011
June, 2011
−
Rev. 4
1
Publication Order Number:
NB4N855S/D
NB4N855S
D0
D0
D1
D1
GND
1
2
3
4
5
10
9
8
7
6
V
CC
Q0
Q0
Q1
Q1
Figure 2. Pin Configuration and Block Diagram
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
Name
D0
D0
D1
D1
GND
Q1
Q1
Q0
Q0
V
CC
I/O
LVPECL, CML, LVCMOS,
LVTTL, LVDS
LVPECL, CML, LVCMOS,
LVTTL, LVDS
LVPEL, CML, LVDS LVCMOS,
LVTTL
LVPECL, CML, LVDS
LVCMOS LVTTL
−
LVDS Output
LVDS Output
LVDS Output
LVDS Output
−
Description
Noninverted Differential Clock/Data D0 Input.
Inverted Differential Clock/Data D0 Input.
Noninverted Differential Clock/Data D1 Input.
Inverted Differential Clock/Data D1 Input.
Ground. 0 V.
Inverted Q1 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Noninverted Q1 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Inverted Q0 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Noninverted Q0 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Positive Supply Voltage.
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2
NB4N855S
Table 2. ATTRIBUTES
Characteristics
Moisture Sensitivity (Note 1)
Micro−10
Flammability Rating
ESD Protection
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 1
Value
Pb−Free Pkg
Level 1
UL 94 V−0 @ 0.125 in
> 2 kV
> 200 V
> 1 kV
281
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
OSC
Parameter
Positive Power Supply
Positive Input
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 2)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 4)
<3 Sec @ 248°C
<3 Sec @ 260°C
Micro−10
Micro−10
Micro−10
Condition 1
GND = 0 V
GND = 0 V
Q to Q
Q or Q to GND
Micro−10
V
I
= V
CC
Continuous
Continuous
Condition 2
Rating
3.8
3.8
12
24
−40
to +85
−65
to +150
177
132
40
265
265
Unit
V
V
mA
T
A
T
stg
q
JA
q
JC
T
sol
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power).
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3
NB4N855S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
I
CC
V
th
V
IH
V
IL
V
IHD
V
ILD
V
CMR
V
ID
V
OD
DV
OD
V
OS
DV
OS
V
OH
V
OL
Power Supply Current (Note 3)
Characteristic
Min
Typ
40
Max
53
Unit
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Figures 10 and 12)
Input Threshold Reference Voltage Range (Note 4)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
GND +100
V
th
+ 100
GND
V
CC
−
100
V
CC
V
th
−
100
V
CC
V
CC
−
100
V
CC
−
50
V
CC
450
1.0
25
1375
1.0
1425
900
1075
25
1600
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 11 and 13)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage (V
IHD
−
V
ILD
)
Differential Output Voltage
Change in Magnitude of V
OD
for Complementary Output States (Note 6)
Offset Voltage (Figure 9)
Change in Magnitude of V
OS
for Complementary Output States (Note 6)
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 8)
100
GND
GND + 50
100
mV
mV
mV
mV
LVDS OUTPUTS
(Note 5)
250
0
1125
0
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Dx/Dx at the DC level within V
CMR
and output pins loaded with R
L
= 100
W
across differential.
4. V
th
is applied to the complementary input when operating in single−ended mode.
5. LVDS outputs require 100
W
receiver termination resistor between differential pair. See Figure 8.
6. Parameter guaranteed by design verification not tested in production.
7. V
OH
max = V
OS
max +
½
V
OD
max.
8. V
OL
max = V
OS
min
−
½
V
OD
max.
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NB4N855S
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V; (Note 9)
−40°C
Symbol
V
OUTPP
f
DATA
t
PLH
,
t
PHL
t
SKEW
Characteristic
Output Voltage Amplitude (@ V
INPPMIN
) f
in
≤
1.0 GHz
(Figure 3)
f
in
= 1.5 GHz
Maximum Operating Data Rate
Differential Input to Differential Output
Propagation Delay
Duty Cycle Skew (Note 10)
Within
−Device
Skew (Note 11)
Device to Device Skew (Note 12)
RMS Random Clock Jitter (Note 13)
Deterministic Jitter (Note 14)
Crosstalk Induced Jitter (Note 15)
V
INPP
t
r
t
f
f
in
= 1.0 GHz
f
in
= 1.5 GHz
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
100
Q, Q
50
110
Min
230
200
1.5
330
Typ
350
300
2.5
410
8
10
20
0.5
0.5
6
7
10
20
490
45
35
100
1
1
15
20
25
40
V
CC
−
GND
180
100
50
110
Max
Min
230
200
1.5
330
25°C
Typ
350
300
2.5
410
8
10
20
0.5
0.5
6
7
10
20
490
45
35
100
1
1
15
20
25
40
V
CC
−
GND
180
100
50
110
Max
Min
230
200
1.5
330
85°C
Typ
350
300
2.5
410
8
10
20
0.5
0.5
6
7
10
20
490
45
35
100
1
1
15
20
25
40
V
CC
−
GND
180
Max
Unit
mV
Gb/s
ps
ps
t
JITTER
ps
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
Output Rise/Fall Times @ 250 MHz
(20%
−
80%)
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing V
INPPMIN
with 50% duty cycle clock source and V
CC
−
1400 mV offset. All loading with an external R
L
= 100
W
across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
10. See Figure 7 differential measurement of t
skew
= |t
PLH
−
t
PHL
| for a nominal 50% differential clock input waveform @ 250 MHz.
11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
12. Skew is measured between outputs under identical transition @ 250 MHz.
13. RMS jitter with 50% Duty Cycle clock signal.
14. Deterministic jitter with input NRZ data at PRBS 2
23
−1
and K28.5.
15. Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 2
23
−1
as
an asynchronous signals.
16. Input voltage swing is a single−ended measurement operating in differential mode.
400
OUTPUT VOLTAGE AMPLITUDE (mV)
350
300
250
200
150
100
50
0
85°C
25°C
−40°C
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 3.3 V)
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