Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
Digital PLLs filter jitter from 14 Hz, 28 Hz, 56 Hz,
112 Hz, 224 Hz, 448 Hz or 896 Hz
Automatic hitless reference switching and digital
holdover on reference fail
Four reference inputs configurable as single ended
or differential
Eight LVPECL outputs and four LVCMOS outputs
Ordering Information
ZL30157GGG
ZL30157GGG2
100 Pin CABGA
100 Pin CABGA*
-40
o
C to +85
o
C
Trays
Trays
*Pb Free Tin/Silver/Copper
•
•
•
Eight outputs configurable as LVCMOS or
LVDS/LVPECL/HCSL
Operates from a single crystal resonator or clock
oscillator
Configurable via SPI/I2C interface
Applications
•
•
•
•
10 Gigabit line cards
Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
OTN multiplexers and transponders
SONET/SDH, Fibre Channel, XAUI
•
•
•
•
ZL30157
Osci
Osco
Master Clock
Clock Generator 0 (Precision)
Div A
Div A
Div B
Synthesizer 0
Fs= Bs
0
*Ks
0
*16*Ms
0
/Ns
0
DPLL0
Fr= Br
0
*Kr
0
*Mr
0
/Nr
0
Div B
Div C
Div C
Div D
Div D
Outputs
4 x LVPECL
LVPECL
4 x LVPECL
LVCMOS
2 x LVCMOS
LVCMOS
2 x LVCMOS
hpdiff0_p/n
hpdiff1_p/n
hpdiff2_p/n
hpdiff3_p/n
hpdiff4_p/n
hpdiff5_p/n
hpdiff6_p/n
hpdiff7_p/n
hpoutclk0
hpoutclk1
hpoutclk2
hpoutclk3
Ref0
Differential /
Single Ended
Differential /
Single Ended
Differential /
Single Ended
Differential /
Single Ended
Ref1
Ref2
DPLL1
Fr= Br
1
*Kr
1
*Mr
1
/Nr
1
Clock Generator 1 (General Purpose)
Div A
Div A
Div B
Div B
Div C
Div C
Div D
Div D
Outputs
Differential /
Single Ended
2 x Differential
Differential /
or 4 x Single
Single Ended
Ended
Differential /
Single Ended
2 x Differential
Differential /
or 4 x Single
Single Ended
Ended
outclk0
outclk1
outclk2
outclk3
outclk4
outclk5
outclk6
outclk7
Ref3
JTAG
JTAG
State Machine
Configuration
and Status
Synthesizer 1
Fs= Bs
1
*Ks
1
*8*Ms
1
/Ns
1
Reference Monitors
pwr_b
GPIO
SPI / I
2
C
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2011, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30157
Description
Short Form Data Sheet
The ZL30157 Dual Channel Universal Clock Translator, part of Zarlink's ClockCenter platform of Synchronous
Clock devices, delivers industry leading synchronization performance for high-speed complex applications. The
highly integrated and programmable solution provides translation from any input reference frequency to any output
clock frequency and allows designers to replace multiple components with a single chip, simplifying design and
reducing component count and power. .
The ZL30157 integrates 2 independent digital PLLs, accepts 4 input references and generates 12 programmable
clock outputs. One precision synthesizers generates clocks with jitter performance that can directly drive 10 G PHY
devices. One general purpose synthesizers generates a wide raneg of digital bus clocks.
2
Zarlink Semiconductor Inc.
Short Form Data Sheet
Mechanical Drawing
c Zarlink Semiconductor 2007 All rights reserved.
Package Code
Previous package codes
ISSUE
ACN
DATE
APPRD.
1.0
Zarlink Semiconductor Inc.
ZL30157
3
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visit our Web Site at
www.zarlink.com
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use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
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any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I
2
C components conveys a license under the Philips I
2
C Patent rights to use these components in and I
2
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conforms to the I
2
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Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
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