PCA9704
18 V tolerant SPI 8-bit GPI with maskable INT
Rev. 1 — 10 December 2015
Product data sheet
1. General description
The PCA9704 is a low power 18 V tolerant SPI General Purpose Input (GPI) shift register
designed to monitor the status of switch inputs. It generates an interrupt when one or
more of the switch inputs change state but allows selected inputs to not generate
interrupts using the interrupt masking feature. The input level is recognized as a HIGH
when it is greater than 0.8
V
DD
and as a LOW when it is less than 0.55
V
DD
(minimum
LOW threshold of 2.5 V at 5 V node). The PCA9704 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK. The contents of
the shift register are loaded into the interrupt mask register of the device on the rising
edge of CS.
Each of the input ports has a 18 V breakdown ESD protection circuit, which dumps the
ESD/overvoltage current to ground. When used with a series resistor (minimum 100 k),
the input can connect to a 12 V battery and support double battery, reverse battery, 27 V
jump start and 40 V load dump conditions in automotive applications. Higher voltages can
be tolerated on the inputs depending on the series resistor used to limit the input current.
The INT_EN pin is used to both enable the GPI pins and to enable the INT output pin to
minimize battery drain in cyclically supplied pull-up or pull-down applications. The SDIN
pull-down prevents floating nodes when the device is used in daisy-chain applications.
With both the high breakdown voltage and high ESD, this device is useful for both
automotive (AEC-Q100 compliance available) and mobile applications.
2. Features and benefits
8 general purpose input ports
18 V tolerant input ports with 100 k external series resistor
Input LOW threshold 0.55
V
DD
with minimum of 2.5 V at V
DD
= 4.5 V
Open-drain interrupt output
Interrupt enable pin (INT_EN) disables GPI pins and interrupt output
Interrupt-masking feature allows no interrupt generation from selected inputs
V
DD
range: 4.5 V to 5.5 V
I
DD
is very low 2.5
A
maximum
SPI serial interface with speeds up to 5 MHz
SPI supports daisy-chain connection for large switch numbers
AEC-Q100 compliance available
NXP Semiconductors
PCA9704
18 V tolerant SPI 8-bit GPI with maskable INT
ESD protection exceeds 5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Operating temperature range:
40 C
to +125
C
Offered in TSSOP16 package
3. Applications
Automotive
Body control modules
Electronic control units (for example, for body controller)
Switch monitoring
SBC wake pin extension
Industrial equipment
Cellular telephones
Emergency lighting
4. Ordering information
Table 1.
Ordering information
Topside
marking
PCA9704
Package
Name
TSSOP16
TSSOP16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT403-1
SOT403-1
Type number
PCA9704PW
PCA9704PW/Q900
[1]
PCA9704
[1]
PCA9704PW/Q900 is AEC-Q100 compliant. Contact
i2c.support@nxp.com
for PPAP.
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9704PWJ
Package
TSSOP16
Packing method
Reel 13” Q1/T1
*Standard mark
SMD
Reel 13” Q1/T1
*Standard mark
SMD
Minimum
Temperature
order quantity
2500
T
amb
=
40 C
to +125
C
Type number
PCA9704PW
PCA9704PW/Q900
PCA9704PW/Q900J TSSOP16
2500
T
amb
=
40 C
to +125
C
PCA9704
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 10 December 2015
2 of 26
NXP Semiconductors
PCA9704
18 V tolerant SPI 8-bit GPI with maskable INT
5. Block diagram
V
DD
INT
PCA9704
INT_EN
IN0
INPUT
DFF0
IN1
INPUT
DFF1
SHIFT REGISTER
MASK REGISTER
IN7
INPUT
DFF15
INPUT
STATUS
REGISTER
SDOUT
SDIN
SCLK
CS
20 μA
V
SS
aaa-016387
Fig 1.
Block diagram of PCA9704
6. Pinning information
6.1 Pinning
SDOUT
INT
INT_EN
IN0
IN1
IN2
IN3
V
SS
1
2
3
4
5
6
7
8
002aae025
16 V
DD
15 SDIN
14 SCLK
13 CS
12 IN7
11 IN6
10 IN5
9
IN4
PCA9704PW
PCA9704PW/Q900
Fig 2.
Pin configuration for TSSOP16
PCA9704
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 10 December 2015
3 of 26
NXP Semiconductors
PCA9704
18 V tolerant SPI 8-bit GPI with maskable INT
6.2 Pin description
Table 3.
Symbol
SDOUT
INT
INT_EN
Pin description
Pin
TSSOP16
1
2
3
output
output
input
3-state serial data output; normally high-impedance
open-drain interrupt output (active LOW)
GPI pin enable and interrupt output enable
1 = GPI pin and interrupt output are enabled
0 = GPI pin and interrupt output are disabled and interrupt
output is high-impedance
IN0
IN1
IN2
IN3
V
SS
IN4
IN5
IN6
IN7
CS
SCLK
SDIN
V
DD
4
5
6
7
8
9
10
11
12
13
14
15
16
input
input
input
input
ground
input
input
input
input
input
input
input
supply
input port 0
input port 1
input port 2
input port 3
ground supply
input port 4
input port 5
input port 11
input port 12
chip select (active LOW)
serial input clock
serial data input (20
A
pull-down)
supply voltage
Type
Description
PCA9704
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 10 December 2015
4 of 26
NXP Semiconductors
PCA9704
18 V tolerant SPI 8-bit GPI with maskable INT
7. Functional description
PCA9704 is a 8-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 k series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes, the input is not masked and the interrupt output is
enabled. The open-drain interrupt output is enabled when INT_EN is HIGH and disabled
when INT_EN is LOW. The INT_EN also enables the GPI pins when it is HIGH. In
cyclically supplied pull-up or pull-down applications, the GPI pull-ups or pull-downs should
be active before the INT_EN is taken HIGH and the INT output should only be sampled
after transient conditions have settled. Additionally, interrupts can be disabled in software
by using the interrupt mask feature. The input port status is accessed via the 4-wire SPI
interface.
Upon power-up, the power-up reset cell clears all the registers, resulting in all zeros in
both the input status register and the interrupt mask register. Since a zero in the interrupt
mask register masks the interrupt from that pin, there will not be any interrupts generated.
After power-up it is necessary to access the PCA9704 through the SPI pins in order to
activate the interrupt for any GPI pins. When the PCA9704 is read over the SPI wires, the
input conditions are clocked into the input status register on the CS falling edge. Since the
inputs and the input status register now match, no interrupt is generated and any
pre-existing interrupt is cleared. The input status register data is parallel loaded into the
shift register on the first rising edge of the SCLK. The serial input data is captured on the
opposite clock edge so that there is a
1
⁄
2
clock cycle hold time. The set-up time is
diminished by the propagation time so the SCLK falling edge to rising edge must be long
enough to provide sufficient set-up time. Successive clock cycles on the SCLK pin clock
the data out of the PCA9704 and new data from the SDIN into the shift register. There is
no limit to the number of clock cycles that can be applied with the CS LOW, however
sufficient clock cycles should be used to both shift out all of the GPI data and shift in the
new interrupt mask data to the correct position with the MSB first before the CS rising
edge.
For cyclic switch bias applications the switch bias should be applied first, then after the
input voltage is settled the general purpose inputs are switched on by taking the INT_EN
HIGH. This also enables the interrupt output, which will only indicate an interrupt if the GPI
data does not match the input status register on a bit that is enabled by the interrupt mask
register value. If an interrupt is generated, the pull-up or pull-down source should remain
active and the INT_EN should remain active and the SPI pins are used to update the input
status register and read the data out. They are also used to store the new interrupt mask
on the rising edge of CS. After the SPI transaction is complete the INT_EN is taken LOW
to turn the inputs off and disable the INT output. Then the GPI pull-ups or pull-downs can
be turned off. The GPI pins are specifically designed so that any ESD/overstress current
flows to ground, not V
DD
. They are also specifically designed so that if the input voltage
returns to the same value after pull-up or pull-down bias cycling as before the input pull-up
or pull-down bias cycling, before the input is enabled it will be detected as the same state.
If the Input Status register is read when INT_EN is LOW, the input state at the INT_EN
transition will be output regardless of the actual input levels since the GPI pins are turned
off.
PCA9704
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 10 December 2015
5 of 26
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