SY89844U
Precision LVDS Runt Pulse Eliminator 2:1
MUX with 1:2 Fanout and Internal Termination
General Description
The SY89844U is a low jitter LVDS, 2:1 input
multiplexer (MUX) optimized for redundant source
switchover
applications.
Unlike
standard
multiplexers, the SY89844U unique 2:1 Runt Pulse
Eliminator (RPE) MUX prevents any short cycles or
“runt” pulses during switchover. In addition, a unique
Fail-Safe Input protection prevents metastable
conditions when the selected input clock fails to a
DC voltage (voltage between the pins of the
differential input drops below 100mV).
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows customers
to interface to any differential signal (AC- or DC-
coupled) as small as 100mV (200mV
pp
) without any
level shifting or termination resistor networks in the
signal path. The outputs are 325mV LVDS with fast
rise/fall times guaranteed to be less than 150ps.
The SY89844U operates from a 2.5V ±5% supply
and is guaranteed over the full industrial
temperature range of –40°C to +85°C. The
SY89844U is part of Micrel’s high-speed, Precision
®
Edge product line.
All support documentation can be found on Micrel’s
web site at:
www.micrel.com.
Precision Edge
®
Features
•
Selects between two sources, and provides a
glitch-free, stable LVDS output
•
Guaranteed AC performance over temperature
and supply voltage:
– wide operating frequency: 1kHz to >1.5GHz
– <870ps In-to-Out t
pd
– <150ps t
r
/t
f
•
Unique patent-pending input isolation design
minimizes crosstalk
•
Fail-Safe Input prevents oscillations
•
Ultra-low jitter design:
– <1ps
RMS
random jitter
– <1ps
RMS
cycle-to-cycle jitter
– <10ps
PP
total jitter (clock)
– <0.7ps
RMS
MUX crosstalk induced jitter
•
Unique patent-pending input termination and VT
pin accepts DC- and AC-coupled inputs (CML,
PECL, LVDS)
•
325mV LVDS output swing
•
2.5V +5% power supply
•
–40°C to +85°C industrial temperature range
•
Available in 24-pin (4mm x 4mm) QFN package
Applications
•
Redundant clock switchover
•
Fail-safe clock protection
Markets
•
•
•
•
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
LAN/WAN
Enterprise servers
ATE
Test and measurement
May 2007
M9999-052207-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89844U
Typical Application
Simplified Example Illustrating Runt Pulse Eliminator
(RPE) when Primary Clock Fails
May 2007
2
M9999-052207-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89844U
Ordering Information
(1)
Part Number
SY89844UMG
SY89844UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals Only.
2. Tape and Reel.
(2)
Package
Type
QFN-24
QFN-24
Operating
Range
Industrial
Industrial
Package Marking
844U with Pb-Free bar-line Indicator
844U with Pb-Free bar-line Indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
24-Pin QFN
May 2007
3
M9999-052207-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89844U
Pin Description
Pin Number
5, 2
23, 20
Pin Name
IN0, /IN0,
IN1, /IN1
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV
(200mVpp). Each pin of a pair internally terminates to a VT pin through 50Ω.
Please refer to the “Input Interface Applications” section for more details.
Reference Voltage: These outputs bias to V
CC
–1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source
current is ±1.5mA. Due to the limited drive capability, the VREF-AC pin is only
intended to drive its respective VT pin. Please refer to the “Input Interface
Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. Please refer to the “Input Interface Applications”
section for more details.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close
to the VCC pins as possible.
Differential Outputs: These LVDS differential output pairs are a logic function of
the IN0, IN1, and SEL inputs. Please refer to the “Truth Table” section below for
details.
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k
Ω pull-up
resistor
and will default to logic HIGH state if left open.
Ground: Ground and exposed pad must be connected to the same ground plane.
Power-On Reset (POR) Initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure
the internal RPE logic starts up in a known state. See “Power-On Reset (POR)
Description” section for more details regarding capacitor selection. If this pin is
tied directly to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. The CAP pin should never be left open.
3, 21
VREF-AC0
VREF-AC1
4, 22
1, 6, 9, 10,
13, 19, 24
7, 8
11, 12
15
14, 17, 18
VT0, VT1
VCC
Q0, /Q0
Q1, /Q1
SEL
GND
Exposed Pad
16
CAP
Truth Table
Inputs
IN0
0
1
X
X
/IN0
1
0
X
X
IN1
X
X
0
1
/IN1
X
X
1
0
SEL
0
0
1
1
Outputs
Q
0
1
0
1
/Q
1
0
1
0
May 2007
4
M9999-052207-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89844U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .......................... –0.5V to +4.0V
Input Voltage (V
IN
) ..................................–0.5V to V
CC
Input Current
Source or sink current on IN, /IN .............. ±50mA
Termination Current
Source or sink current on V
T
.................. ±100mA
V
REF-AC
Source or sink current ........................... ±2mA
Lead Temperature (soldering, 20 sec.) .......... +260°C
Storage Temperature (T
s
) ..................–65°C to 150°C
Operating Ratings
(2)
Supply Voltage (V
CC
).................. +2.375V to +2.625V
Ambient Temperature (T
A
) ................ –40°C to +85°C
(3)
Package Thermal Resistance
QFN (θ
JA
)
Still-Air ..................................................... 50°C/W
QFN (ψ
JB
)
Junction-to-Board .................................... 30°C/W
DC Electrical Characteristics
(4)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
IN_FSI
V
T_IN
V
REF-AC
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
θ
JA
and
ψ
JB
values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V
IN
(max) is specified when V
T
is floating.
Parameter
Power Supply
Power Supply Current
Input Resistance
(IN-to-V
T
)
Differential Input Resistance
(IN-to-/IN)
Input High Voltage
(IN, /IN)
Input Low Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
|IN-/IN|
Input Voltage Threshold that
Triggers FSI
IN-to-V
T
(IN, /IN)
Output Reference Voltage
Condition
No load, max V
CC
Min
2.375
45
90
1.2
0
Typ
2.5
105
50
100
Max
2.625
140
55
110
V
CC
V
IH
–0.1
V
CC
Units
V
mA
Ω
Ω
V
V
V
V
See Figure 1a. Note 5.
See Figure 1b.
0.1
0.2
30
100
1.28
mV
V
V
V
CC
–1.3
V
CC
–1.2
V
CC
–1.1
May 2007
5
M9999-052207-B
hbwhelp@micrel.com
or (408) 955-1690
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