531SB1071M00DGR datasheet, PDF

Datasheet> All Categories > oscillator> 531SB1071M00DGR

531SB1071M00DGR: DescriptionLVDS Output Clock Oscillator, 1071MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531SB1071M00DGR Overview

LVDS Output Clock Oscillator, 1071MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531SB1071M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1071 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Principle circuit diagram of monitoring acid rain acidity

New Current Drive Amplifier 02

Simple hysteresis-free dimming circuit

Micro lead-acid battery adjustable charger circuit

Infrared modulation detection circuit

820e computer motherboard circuit diagram_35

stm32 register boundary address problem: As shown in the red box in the picture, taking GPIOF as an example, its boundary address is 0x40021400 - 0x400217FF. By calculation, it can be concluded that the address size is 0x3FF bytes. Regardles...; luzhangcheng MCU

【Gravity:AS7341 Review】+First Look at AS7341: The logistics is quite fast, and it was delivered to me very quickly. I have been a little busy these days, so I haven't used it yet. But the appearance is OK, and the sensor is smaller than I expecte...; han0097 Domestic Chip Exchange

Why can’t I find the daily report this morning?: Why can't I find the daily report this morning! :)January 13Report in the morning on a sunny day...; jameswangsynnex Talking

Several problems with assembly instructions, please help solve them: strneb r2,[r3,r4] means send address r3+address r4 to r2 or send address r3+address r4 to r2 ldr r0,[r1],#4 means send the value of r0 to address r1, address r1+4 or send the value of r0 to address r1...; haoya84 Embedded System

I'm looking for a communication program between VC and 51 microcontroller or a Cambridge Bluetooth program.: 1(T1in)--->14(T1out) Rx In vc, I use API functions to communicate with the serial port. I want to use hardware stream DTR/DSR to control the communication of the serial port. The general idea is as fo...; Jonsen_yang Embedded System

With 6 development boards per person and over 10,000 yuan in prize money, ON Semiconductor and Avnet's IoT Innovation Design Competition is waiting for you to join!: Friends, if you are given an ultra-low-power Bluetooth 5.0 system, including Arduino connectors, temperature monitoring, multiple sensors and simulators, combined with your creativity, what kind of sm...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components