EP1C6Q100I8ES datasheet, PDF - EEWORLD Datasheet

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EP1C6Q100I8ES: DescriptionFPGA, 5980 CLBS, 275 MHz, PQFP144; Categorysemiconductor Programmable logic devices; File Size755KB，104 Pages; ManufacturerAltera (Intel)

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EP1C6Q100I8ES Overview

FPGA, 5980 CLBS, 275 MHz, PQFP144

EP1C6Q100I8ES Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
organize	5980 CLBS
Maximum FCLK clock frequency	275 MHz
Number of configurable logic modules	5980
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY

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Section I. Cyclone FPGA

Family Data Sheet

This section provides designers with the data sheet specifications for

Cyclone

devices. The chapters contain feature definitions of the internal

architecture, configuration and JTAG boundary-scan testing information,

DC operating conditions, AC timing parameters, a reference to power

consumption, and ordering information for Cyclone devices.

This section contains the following chapters:

■

Chapter 1. Introduction

Chapter 2. Cyclone Architecture

Chapter 3. Configuration & Testing

Chapter 4. DC & Switching Characteristics

Chapter 5. Reference & Ordering Information

Revision History

Refer to each chapter for its own specific revision history. For information

on when each chapter was updated, refer to the Chapter Revision Dates

section, which appears in the complete handbook.

Altera Corporation

Section I–1

Preliminary

1. Introduction

C51001-1.4

Introduction

The Cyclone

field programmable gate array family is based on a 1.5-V,

0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost-effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 640 megabits per second (Mbps), and 66- and

33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for

interfacing with and supporting ASSP and ASIC devices. Altera also

offers new low-cost serial configuration devices to configure Cyclone

devices.

The following shows the main sections in the Cyclone FPGA Family Data

Sheet:

Section

Page

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Global Clock Network & Phase-Locked Loops. . . . . . . . . . . 2–29

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . . 2–55

IEEE Std. 1149.1 (JTAG) Boundary Scan Support . . . . . . . . . . 3–1

SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Altera Corporation

January 2007

1–1

Preliminary

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