dsPIC33FJXXXGPXXX/
dsPIC33FJXXXMCXXX
dsPIC33F Rev. A2 Silicon Errata
dsPIC33FJXXXGPXXX,
dsPIC33FJXXXMCXXX
(Rev. A2) Silicon Errata
The dsPIC33F devices (Rev. A2) you received were
found to conform to the specifications and functionality
described in the following documents:
• DS70165 – “dsPIC33F
Family Data Sheet”
• DS70157 – “dsPIC30F/33F
Programmer’s
Reference Manual”
• DS70046 –
“dsPIC30F Family Reference Manual”
The exceptions to the specifications in the documents
listed above are described in this section. The specific
devices for which these exceptions are described are
listed below:
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dsPIC33FJ64GP206
dsPIC33FJ64GP306
dsPIC33FJ64GP310
dsPIC33FJ64GP706
dsPIC33FJ64GP708
dsPIC33FJ64GP710
dsPIC33FJ128GP206
dsPIC33FJ128GP306
dsPIC33FJ128GP310
dsPIC33FJ128GP706
dsPIC33FJ128GP708
dsPIC33FJ128GP710
dsPIC33FJ256GP506
dsPIC33FJ256GP510
dsPIC33FJ256GP710
dsPIC33FJ64MC506
dsPIC33FJ64MC508
dsPIC33FJ64MC510
dsPIC33FJ64MC706
dsPIC33FJ64MC710
dsPIC33FJ128MC506
dsPIC33FJ128MC510
dsPIC33FJ128MC706
dsPIC33FJ128MC708
dsPIC33FJ128MC710
dsPIC33FJ256MC510
dsPIC33FJ256MC710
dsPIC33F Rev. A2 silicon is identified by performing a
“Reset and Connect” operation to the device using
MPLAB
®
ICD 2 with MPLAB IDE v7.40 or later. The
output window will show a successful connection to the
device specified in
Configure>Select Device.
The errata described in this section will be addressed
in future revisions of silicon.
Silicon Errata Summary
The following list summarizes the errata described in
further detail through the remainder of this document:
1.
Doze Mode
When Doze mode is enabled, any writes to a
peripheral SFR can cause other updates to that
register to cease to function for the duration of the
current CPU clock cycle.
2.
12-bit Analog-to-Digital Converter (ADC) Module
For this revision of silicon, the 12-bit ADC module
INL, DNL and signal acquisition time parameters
are not within the published data sheet
specifications.
3.
10-bit ADC Module
For this revision of silicon, the 10-bit ADC module
DNL, conversion speed and signal acquisition time
parameters are not within the published data sheet
specifications.
4.
DMA Module: Interaction with
EXCH
Instruction
The
EXCH
instruction does not execute correctly
when one of the operands contains a value equal
to the address of the DMAC SFRs.
5.
DISI
Instruction
The
DISI
instruction will not disable interrupts if a
DISI
instruction is executed in the same instruc-
tion cycle that the
DISI
counter decrements to
zero.
6.
Motor Control PWM
There is a glitch in the PWMxL signal in Single-
Shot mode with complementary output. Another
glitch occurs when resuming from a Fault condition
in Free-Running mode with complementary
output.
©
2006 Microchip Technology Inc.
DS80279B-page 1
dsPIC33F
7.
Output Compare Module
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
8.
Output Compare Module in PWM Mode
The output compare module will miss one com-
pare event when the duty cycle register value is
updated from 0x0000 to 0x0001.
9.
SPI Module in Frame Master Mode
The SPI module will fail to generate frame
synchronization pulses in Frame Master mode.
10. SPI Module in Slave Select Mode
The SPI module Slave Select functionality will not
work correctly.
11. SPI Module
The SMP bit does not have any effect when the
SPI module is configured for a 1:1 prescale factor
in Master mode.
12. ECAN™ Module
ECAN transmissions may be incorrect if multiple
transmit buffers are simultaneously queued for
transmission.
13. ECAN Module
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the transmit buffer ID register.
14. ECAN Module Loopback Mode
The ECAN module (ECAN1 or ECAN2) does not
function correctly in Loopback mode.
15. I
2
C™ Module
The bus collision status bit does not get set when
a bus collision occurs during a Restart or Stop
event.
16. INT0, ADC and Sleep/Idle Mode
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep or Idle mode if the
SMPI bits are non-zero.
17. Doze Mode and Traps
The address error trap, stack error trap, math error
trap and DMA error trap will not wake-up a device
from Doze mode.
18. JTAG Programming
JTAG programming does not work.
The following sections will describe the errata and work
around to these errata, where they may apply.
1. Module: Oscillator: Doze Mode
Enabling Doze mode slows down the CPU but
allows peripherals to run at full speed. When the
CPU clock is slowed down by enabling Doze mode
(CLKDIV<11> =
1),
any writes to a peripheral SFR
can cause other updates to that register to cease
to function for the duration of the current CPU
clock cycle. This is only an issue if the CPU
attempts to write to the same register as a
peripheral while in Doze mode.
For instance, if the ADC module is active and Doze
mode is enabled, the main program should avoid
writing to ADCCONx registers because these reg-
isters are being used by the ADC module. If the
CPU does make writes before the ADC module
does, then any attempts by the ADC module to
write to these registers will fail.
Work around
In Doze mode, avoid writing code that will modify
SFRs which may be written to by enabled
peripherals.
DS80279B-page 2
©
2006 Microchip Technology Inc.
dsPIC33F
2. Module: 12-bit ADC
When the ADC module is configured for 12-bit
operation, the specifications in the data sheets are
not met.
Work around
Implement the ADC module as an 11-bit ADC with
a maximum conversion rate of 300 Ksps.
1. The specifications provided below reflect 11-bit
ADC operation. RIN source impedance is rec-
ommended as 200 ohms and sample time is
recommended as 3 T
AD
to ensure compatibility
on future enhanced ADC modules. Missing
codes are possible every 2
7
codes.
2. When used as a 10-bit ADC, the INL is <±2
LSBs, and DNL is <±1 LSB with no missing
codes. Maximum conversion rate is 300 Ksps.
TABLE 1:
Param No.
AD17
AD20a
AD21a
AD22a
AD23a
AD24a
AD21aa
AD22aa
AD23aa
AD24aa
AD33a
AD34a
AD56a
AD57a
ADC PERFORMANCE (11-BIT OPERATION)
Symbol
RIN
Nr
INL
DNL
GERR
EOFF
INL
DNL
GERR
EOFF
FNYQ
ENOB
FCNV
TSAMP
Min
—
—
-2
-1.5
1
1
-2
-1.5
5
3
—
9.5
—
—
Typical
—
12 bits
—
—
5
3
—
—
10
6
—
9.6
—
3 T
AD
Max
200
—
2
1
10
6
2
1
20
15
150
10.4
300
—
Units
Ohm
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
KHz
Bits
Ksps
—
Conditions
12-bit
ADC Accuracy – Measurements taken with External V
REF
+/V
REF
-
ADC Accuracy – Measurements taken with Internal V
REF
+/V
REF
-
Dynamic Performance
ADC Conversion Rate
©
2006 Microchip Technology Inc.
DS80279B-page 3
dsPIC33F
3. Module: 10-bit ADC
When the ADC module is configured for 10-bit
operation, the specifications in the data sheet are
not met for operation above 500 Ksps.
For 500 Ksps, the module meets specifications
except for Gain and Offset parameters AD23bb
and AD24bb.
For 600 Ksps operation, the module specifications
are shown in Table 2.
Work around
None. Future versions of the silicon will support
the ADC performance stated in the data sheet.
TABLE 2:
Param No.
AD17
AD20b
AD21b
AD22b
AD23b
AD24b
AD21bb
AD22bb
AD23bb
AD24bb
AD33b
AD34b
AD56b
AD57b
600 KSPS OPERATION
Symbol
RIN
Nr
INL
DNL
GERR
EOFF
INL
DNL
GERR
EOFF
FNYQ
ENOB
FCNV
TSAMP
Min
—
—
-2
-1.5
1
1
-2
-1.5
1
2
—
8.5
—
—
Typ
—
10 bits
—
—
3
2
—
—
6
5
Dynamic Performance
—
9.7
ADC Conversion Rate
—
3 T
AD
600
—
Ksps
—
300
9.8
KHz
Bits
Max
200
—
2
2
6
5
2
2
12
10
Units
Ohm
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Conditions
10-bit
ADC Accuracy – Measurements taken with External V
REF
+/V
REF
-
ADC Accuracy – Measurements taken with Internal V
REF
+/V
REF
-
4. Module: DMA Module: Interaction with
EXCH
Instruction
The
EXCH
instruction does not execute correctly
when either of the two operands is numerically
equal to the address of any of the DMAC SFRs for
this revision of silicon.
Work around
If writing source code in assembly, the
recommended fix is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, check the dis-
assembly listing (View>Disassembly
Listing)
for
the
EXCH
instruction. If used, make sure the oper-
ands are not equivalent to the DMA SFRs’
addresses.
DS80279B-page 4
©
2006 Microchip Technology Inc.
dsPIC33F
5. Module:
DISI
Instruction
When a user executes a
DISI
#7, for example,
this will disable interrupts for 7 + 1 cycles (7 + the
DISI
instruction itself). In this case, the
DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the
DISI
instruction.
If the user code executes another
DISI
on the
instruction cycle where the
DISI
counter has
become zero, the new
DISI
count is loaded, but
the
DISI
state machine does not properly re-
engage and continue to disable interrupts. At this
point, all interrupts are enabled. The next time the
user code executes a
DISI
instruction, the feature
will act normally and block interrupts.
In summary, it is only when a
DISI
execution is
coincident with the current
DISI
count =
0,
that the
issue occurs. Executing a
DISI
instruction before
the
DISI
counter reaches zero will not produce
this error. In this case, the
DISI
counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple
DISI
instructions within
the source code, make sure that subsequent
DISI
instructions have at least one instruction cycle
between the time that the
DISI
counter decre-
ments to zero and the next
DISI
instruction. Alter-
natively, make sure that subsequent
DISI
instructions are called before the
DISI
counter
decrements to zero.
7. Module: Output Compare Module
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
high using the output compare module or a
write to the associated PORT register.
• The output compare module is configured and
enabled to drive the pin low at some later time
(OCxCON = 0x0002 or OCxCON = 0x0003).
When these events occur, the output compare
module will drive the pin low for one instruction
cycle (T
CY
) after the module is enabled.
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
8. Module: Output Compare Module in PWM
Mode
The output compare module will miss a compare
event when the current duty cycle register
(OCxRS) value is 0x0000 (0% duty cycle) and the
OCxRS register is updated with a value of 0x0001.
The compare event is missed only the first time a
value of 0x0001 is written to OCxRS, and the
PWM output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
None. If the current OCxRS register value is
0x0000, avoid writing a value of 0x0001 to
OCxRS. Instead, write a value of 0x0002; how-
ever, in this case the duty cycle will be slightly
different from the desired value.
6. Module: Motor Control PWM
Devices in the motor control family have a glitch in
the PWMxL signal under certain conditions. The
glitch is a brief high pulse during the low portion of
the duty cycle. This error occurs when the module
is configured in Single-Shot mode (PTMOD<1:0>
=
01)
with complementary output. It also occurs
when resuming from a Fault condition in
Free-Running mode (PTMOD<1:0) =
00)
with
complementary output.
Work around
None.
©
2006 Microchip Technology Inc.
DS80279B-page 5
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