Rev 2; 4/08
106.25MHz/212.5MHz/425MHz
Clock Oscillators
General Description
The DS4106, DS4212, and DS4425 ceramic surface-
mount crystal oscillators are part of Maxim’s DS4-XO
series of crystal oscillators. These devices offer output
frequencies at 106.25MHz, 212.5MHz, and 425MHz.
The clock oscillators are suited for systems with tight tol-
erances because of the jitter, phase noise, and stability
performance. The small package provides a format
made for applications where PCB space is critical.
These clock oscillators are crystal based and use a fun-
damental crystal with PLL technology to provide the
final output frequencies. Each device is offered with
LVDS or LVPECL output types. The output enable pin is
active-high logic.
These clock oscillators have very low phase jitter and
phase noise. Typical phase jitter is < 0.9ps RMS from
12kHz to 20MHz. The devices are designed to operate
with a 3.3V ±10% supply voltage, and are available in a
5.0mm x 3.2mm x 1.49mm, 10-pin LCCC surface-mount
ceramic package.
♦
Clock Output Frequencies:
DS4106: 106.25MHz
DS4212: 212.50MHz
DS4425: 425.00MHz
♦
Phase Jitter (RMS): 0.9ps Typical
♦
LVPECL or LVDS Output
♦
Supply Current:
50mA (Typical, Unloaded) at +3.3V Supply
(LVPECL)
53mA (Typical) at +3.3V Supply (LVDS)
♦
-40°C to +85°C Temperature Range
♦
Output Disable
Features
DS4106/DS4212/DS4425
Ordering Information
PART
DS4106AN+
DS4106BN+
DS4212AN+
DS4212BN+
DS4425AN+
DS4425BN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
Applications
Fibre Channel Hard Disk Drives
Host Bus Adapters
Raid Controllers
Fibre Channel Switches
Pin Configuration and Selector Guide appear at end of
data sheet.
+Denotes
a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Typical Operating Circuits
V
CC
V
CC
OE
OUTP
50Ω
V
CC
OE
V
CC
V
CC
OUTP
V
CC
DS4106/
DS4212/
DS4425
OUTN
GND
V
CC
- 2V
50Ω
100Ω
LVPECL
DS4106/
DS4212/
DS4425
OUTN
GND
100Ω
LVDS
LVPECL OPTION
LVDS OPTION
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
106.25MHz/212.5MHz/425MHz
Clock Oscillators
DS4106/DS4212/DS4425
ABSOLUTE MAXIMUM RATINGS
V
CC
, GND, OE, OUTP, OUTN .....................................-0.3V, +4V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-40°C to +125°C
Soldering Temperature Profile
(3 passes max) ...............................See IPC/JEDEC J-STD-020
Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C, typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
Supply Current
TTL Control Input-Voltage High
(OE)
TTL Control Input-Voltage Low
(OE)
Input Leakage Current
LVPECL OUTPUTS (Note 4)
Output High Voltage
Output Low Voltage
Output Leakage Current
(Absolute)
LVDS OUTPUTS (Figure 2)
LVDS Output High Voltage
LVDS Output Low Voltage
LVDS Differential Output Voltage
LVDS Change in V
OD
for
Complementary States
LVDS Offset Output Voltage
(Output Common-Mode Voltage)
V
OH
V
OL
|V
OD
|
|
V
OD
|
V
OS
(Note 5)
1.125
(Note 2)
(Note 2)
0.925
250
400
25
1.275
mV
1.475
V
V
V
OH
V
OL
I
OL
(Note 2)
(Note 2)
OE = V
IL
V
CC
- 1.085
V
CC
- 1.825
100
V
CC
- 0.88
V
CC
- 1.62
V
V
μA
SYMBOL
V
CC
I
CC
V
IH
V
IL
I
IL
(Note 2)
LVPECL (Note 3)
LVDS
(Note 2)
(Note 2)
GND
OE
V
CC
2
0
-50
CONDITIONS
MIN
3.0
TYP
3.3
50
53
MAX
3.6
65
67
V
CC
0.8
+10
UNITS
V
mA
V
V
μA
V
2
_______________________________________________________________________________________
106.25MHz/212.5MHz/425MHz
Clock Oscillators
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C, typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
LVDS Change in V
OS
for
Complementary States
LVDS Differential Output
Impedance
LVDS Output Current
Output Current
CLOCK OUTPUT
DS4106
Clock Output Frequency
Frequency Stability Total
Initial Frequency Tolerance
Frequency Stability vs.
Temperature
Frequency Stability vs. V
CC
Frequency Stability vs. Load
Aging (15 Years)
Phase Jitter (RMS)
Accumulated Deterministic
Jitter Due to Power-Supply Noise
(P-P)
f
O
f / f
O
f
_TOL
f / f
O
|
TA
f / f
O
|
V
f / f
O
|
LOAD
f
AGING
PJ
RMS
12kHz to 20MHz
10kHz
100kHz
200kHz
1MHz
Clock Output Edge Speeds
Clock Output Duty Cycle
Oscillation Startup Time
t
R
, t
F
20% to 80%
+25°C
(Note 6)
LVPECL
LVDS
45
10
V
CC
= 3.3V
±10%
±10%
variation in termination
resistance
-7
0.9
3
27
15
7
200
175
55
ps
%
ms
ps
DS4212
DS4425
Temperature, aging, load, and supply
+25°C,
±3°C,
V
CC
= 3.3V
-30
-3
±1
+7
-39
±20
+30
+3
106.25
212.5
425.0
+39
ppm
ppm
ppm
ppm/V
ppm
ppm
ps
MHz
SYMBOL
|
V
OS
|
R
OLVDSO
I
LVDSO
Outputs shorted together
80
12
40
CONDITIONS
MIN
TYP
MAX
150
140
mA
mA
UNITS
mV
DS4106/DS4212/DS4425
I
VSSLVDSO
Short to ground
_______________________________________________________________________________________
3
106.25MHz/212.5MHz/425MHz
Clock Oscillators
DS4106/DS4212/DS4425
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, T
A
= -40°C to +85°C, typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
100Hz
1kHz
DS4106 at 106.25MHz
10kHz
100kHz
1MHz
10MHz
100Hz
1kHz
Clock Output SSB Phase Noise
DS4212 at 212.50MHz
10kHz
100kHz
1MHz
10MHz
100Hz
1kHz
DS4425 at 425.00MHz
10kHz
100kHz
1MHz
10MHz
MIN
TYP
-90
-112
-115
-123
-142
-147
-82
-106
-109
-117
-136
-141
-76
-100
-103
-111
-130
-135
dBc/Hz
MAX
UNITS
Limits at -40°C are guaranteed by design and are not production tested.
Voltage referenced to ground.
Outputs are enabled and unloaded.
When the LVPECL output is disabled, the typical output off current is < 100µA for nominal LVPECL signal levels at the
output.
Note 5:
AC parameters are guaranteed by design and characterization.
Note 6:
Including oscillator startup time and PLL acquisition time, measured after V
CC
reaches 3.0V from power-on.
Note 1:
Note 2:
Note 3:
Note 4:
4
_______________________________________________________________________________________
106.25MHz/212.5MHz/425MHz
Clock Oscillators
Pin Description
PIN
NAME
FUNCTION
Output Enable. On-chip pullup resistor. Connect OE to logic-high, V
CC
, or leave open to enable the
output clock. Connect OE to logic-low or GND to disable the output clock. The LVPECL output
clock is set to high impedance when disabled. The LVDS output clock is latched to a differential
high when disabled.
No Connection
Ground
Positive Clock Output, LVPECL or LVDS
Negative Clock Output, LVPECL or LVDS
+3.3V Supply
Exposed Paddle. Do not connect this pad or place exposed metal under the pad.
DS4106/DS4212/DS4425
1
OE
2, 7–10
3
4
5
6
—
N.C.
GND
OUTP
OUTN
V
CC
EP
Detailed Description
The DS4106/DS4212/DS4425 combine a crystal and an
IC to form a precision clock. Figure 1 shows a function-
al diagram of the devices. The IC consists of a crystal
oscillator, a low-noise PLL, selectable clock-divider cir-
cuitry, and an output buffer. The PLL consists of a digi-
tal phase/frequency detector (PFD) and low-jitter
generation VCO. The VCO signal is scaled by a clock-
divider circuit and applied to the output buffer.
Output Drivers
All devices are available with either LVPECL
(DS4106A/DS4212A/DS4425A) or LVDS (DS4106B/
DS4212B/DS4425B) output buffers. When not needed,
the output buffers can be disabled. When disabled, the
LVPECL output buffer goes to a high-impedance state.
However, the LVDS outputs go to a differential logic
one (OUTP latched high and OUTN latched low) when
the outputs are disabled.
Additional Information
For more available frequencies, refer to the DS4125
data sheet at
www.maxim-ic.com/DS4125.
V
CC
OUTP
OSCILLATOR
AMPLIFIER
PFD
LOOP FILTER
VCO
COUNTER M
OUTPUT
BUFFER
OUTN
V
CC
DS4106/
DS4212/
DS4425
COUNTER N
OE
GND
Figure 1. Functional Diagram
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