DS1013S-70 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> DS1013S-70

DS1013S-70: DescriptionSILICON DELAY LINE, TRUE OUTPUT, PDIP14; Categorylogic logic; File Size50KB，6 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

Download Datasheet Parametric View All

DS1013S-70 Overview

SILICON DELAY LINE, TRUE OUTPUT, PDIP14

DS1013S-70 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Reach Compliance Code	unknow
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
Number of functions	3
Number of taps/steps	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Maximum supply current (ICC)	70 mA
programmable delay line	NO
Prop。Delay @ Nom-Su	70 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Base Number Matches	1

Preview

Download Datasheet

View All

DS1013

3-in-1 Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

3 independent buffered delays

Delay tolerance ±2ns for -10 through –60

Stable and precise over temperature and

voltage range

Leading and trailing edge accuracy

Economical

Auto-insertable, low profile

Standard 14-pin DIP, 8-pin DIP, or 16-pin

SOIC

Low-power CMOS

TTL/CMOS-compatible

Vapor phase, IR and wave solderable

Custom delays available

Quick turn prototypes

Extended temperature ranges available

PIN ASSIGNMENT

IN 1

IN 2

IN 3

GND

OUT 1

OUT 2

IN 1

IN 2

IN 3

OUT 1

OUT 2

OUT 3

OUT 3 GND

DS1013 14-pin DIP (300-mil)

See Mech. Drawings Section

DS1013S 16-pin SOIC

(300-mil)

See Mech. Drawings Section

OUT 1

OUT 2

OUT 3

IN 1

IN 2

IN 3

GND

DS1013M 8-pin DIP (300-mil)

See Mech. Drawings Section

PIN DESCRIPTION

IN 1, IN 2, IN 3

OUT 1, OUT 2, OUT 3

GND

- Inputs

- Outputs

- Ground

- +5 Volts

- No Connection

DESCRIPTION

The DS1013 series of delay lines has three independent logic buffered delays in a single package. The

devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternative

8-pin DIP and surface mount packages are available which save PC board area. Since the DS1013

products are an all silicon solution, better economy is achieved when compared to older methods using

hybrid techniques. The DS1013 series delay lines provide a nominal accuracy of

±2ns

for delay times

ranging from 10 ns to 60 ns, increasing to 5% for delays of 150 ns and longer. The DS1013 delay line

reproduces the input logic state at the output after a fixed delay as specified by the dash number extension

of the part number. The DS1013 is designed to reproduce both leading and trailing edges with equal

precision. Each output is capable of driving up to 10 74LS loads. Dallas Semiconductor can customize

standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.

1 of 6

111799

Recommended Resources

Three electric motors have control circuits required for starting and stopping sequences

QJ3 series manual operation auto-coupling step-down starting circuit

Programmable ROM LED display

Transistor driven TTL interface circuit

Bidirectional thyristor zero-crossing switch circuit diagram

Neon sign color-black and white developing and fixing precision thermostat circuit

The mainstream of power supply technology development: The transistor was invented at the end of 1947, and less than a decade later, the silicon-controlled rectifier (SCR, now called thyristor) was invented based on the gradual maturity of the transistor,...; zbz0529 Power technology

How to solve USB driver conflicts in Linux: I have a USB capture card and a USB capture card driver. I originally planned to modify and write a capture card driver based on the universal driver. The problem is: the system can recognize the USB ...; lzwml Linux and Android

F28377 2P2Z (PID) settings and usage: [size=4]2P2Z is a commonly used power loop compensation algorithm. Here is a brief summary of its use for subsequent use. [/size] [size=4]First, you need to declare the structure: [/size] [size=4][cpp...; Jacktang Microcontroller MCU

Let me share my thoughts on the forum (if I post to the wrong section, please forgive me): I haven't been to the forum for a long time. I was too busy recently. I went online today and found that it is still very popular. It's really good. Although many forums and QQ groups have many people...; 五月一 FPGA/CPLD

Guitar electronics development direction research field: Dear IT experts and colleagues, do you like guitars? I would like to know about the development prospects of electronics related to guitars, such as guitar pickups, etc. Thank you!...; ky0611 TI Technology Forum

MSP430 LaunchPad Timer Interrupt (Continuous Mode): #include msp430g2231.hint main( void ) { // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD;P1DIR |= 0x01;TACCTL0 = CCIE; // Enable the interrupt generated by the CCIFG flagTACC...; Jacktang Microcontroller MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components