INTEGRATED CIRCUITS
80C562/83C562
Single-chip 8-bit microcontroller
Product specification
IC20 Data Handbook
1992 Jan 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
Single-chip 8-bit microcontroller with 8-bit A/D, capture/compare timer, high-speed outputs, PWM
DESCRIPTION
The 80C562/83C562 (hereafter generically
referred to as 8XC562) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83C562/83C562 has the same instruction set
as the 80C51.
The 8XC562 contains a non-volatile 256
×
8
read-only program memory, a volatile 256
×
8
read/write data memory (83C562) (the
80C562 is ROMless), a volatile 256
×
8
read/write data memory, six 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare
latches, a 15-source, two-priority-level,
nested interrupt structure, an 8-input ADC,
two pulse width modulated outputs, standard
80C51 UART, a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that
require extra capability, the 83C562 can be
expanded using standard TTL compatible
memories and logic.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 12MHz crystal, 58% of the
instructions are executed in 1µs and 40% in
2µs. Multiply and divide instructions require
4µs.
FEATURES
•
80C51 instruction set
•
8k
×
8 ROM expandable externally to
64k bytes
PIN CONFIGURATION
9
10
PLASTIC
LEADED
CHIP CARRIER
26
27
43
44
1
61
60
•
256
×
8 RAM, expandable externally to
64k bytes
•
Two standard 16-bit timer/counters
•
An additional 16-bit timer/counter coupled
to four capture registers and three compare
registers
•
Capable of producing eight synchronized,
timed outputs
•
An 8-bit ADC with eight multiplexed analog
inputs
•
Two 8-bit resolution, pulse width modulated
outputs
•
Five 8-bit I/O ports plus one 8-bit input port
shared with analog inputs
•
Full-duplex UART compatible with the
standard 80C51
•
On-chip watchdog timer
•
Three temperature ranges
– 0 to +70°C
– –40 to +85°C
– –40 to +125°C
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
P5.0/ADC0
V
DD
STADC
PWM0
PWM1
EW
P4.0/CMSR0
P4.1/CMSR1
P4.2/CMSR2
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
P1.0/CT0I
P1.1/CT1I
P1.2/CT2I
P1.3/CT3I
P1.4/T2
P1.5/RT2
P1.6
P1.7
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
NC
NC
XTAL2
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
XTAL1
V
SS
V
SS
NC
P2.0/A08
P2.1/A09
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
AVref–
AVref+
AV
SS
AV
DD
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
SU00224
1992 Jan 08
2
853–1463 05128
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
ORDERING INFORMATION
PHILIPS PART
ORDER NUMBER
PART MARKING
ROMless
ROM
PHILIPS NORTH AMERICA
PART ORDER NUMBER
ROMless
ROM
S83C562-4A68
Drawing
Number
SOT188
EPROM
S87C552-4A68
2
S87C552-4K68
2
PCF80C562-
12WP
PCF83C562-
12WP/xxx
S80C562-2A68
S83C562-2A68
SOT188
S87C552-5A68
2
Drawing
Number
SOT188-3
1473A
SOT188-3
TEMPERATURE
RANGE
°C
AND PACKAGE
0 to +70, Plastic
Leaded Chip Carrier
0 to +70, Plastic
Leaded Chip Carrier
w/Window
–40 to +85, Plastic
Leaded Chip
Carrier
–40 to +85, Plastic
Leaded Chip Carrier
w/Window
–40 to +125, Plastic
Leaded Chip Carrier
FREQ
MHz
16
16
12
PCB80C562- PCB83C562-
S80C562-4A68
16WP
16WP/xxx
S87C552-5K68
2
PCA80C562- PCA83C562- S80C562-6A68 S83C562-6A68 SOT188
12WP
12WP/xxx
NOTES:
1. 80C562 and 83C562 frequency range is 1.2MHz–12MHz or 1.2MHz–16MHz.
2. 87C552 frequency range is 3.5MHz–16MHz. For full specification, see the 87C552 data sheets.
3. xxx denotes the ROM code number.
1473A
12
12
LOGIC SYMBOL
V
SS
V
DD
XTAL1
XTAL2
EA
ALE
PSEN
AV
SS
AV
DD
AVref+
AVref–
STADC
PWM0
PWM1
PORT 0
LOW ORDER
ADDRESS AND
DATA BUS
CT0I
CT1I
CT2I
CT3I
T2
RT2
ADC0-7
PORT 5
PORT 2
PORT 1
HIGH ORDER
ADDRESS AND
DATA BUS
CMSR0-5
PORT 4
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
CMT0
CMT1
RST
EW
SU00225
1992 Jan 08
3
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
BLOCK DIAGRAM
T0
3
T1
3
INT0
3
INT1
3
V
DD
V
SS
PWM0
PWM1
AV
SS
AV
REF
ADC0–7
5
– +
AV
DD
STADC
XTAL1
XTAL2
EA
ALE
PSEN
3
3
RD
0
AD0–7
2
A8–15
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
T2
16-BIT
TIMER/
EVENT
COUNTERS
16
16
WR
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
PROGRAM
MEMORY
8k x 8 ROM
(83C562)
DATA
MEMORY
256 x 8 RAM
DUAL
PWM
CPU
ADC
80C51 CORE
EXCLUDING
ROM/RAM
8-BIT INTERNAL BUS
T2
16-BIT
COMPARATORS
WITH
REGISTERS
COMPARATOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
3
P0
P1
P2
P3
TxD
3
RxD
P5
P4
1
CT0I–CT3I
1
T2
RT2
1
4
CMSR0–CMSR5
CMT0, CMT1
RST
EW
0
1
2
ALTERNATE FUNCTION OF PORT 0
ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2
3
4
5
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
SU00226
1992 Jan 08
4
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
PIN DESCRIPTION
MNEMONIC
V
DD
STADC
PWM0
PWM1
EW
P0.0–P0.7
PIN NO.
2
3
4
5
6
57–50
TYPE
I
I
O
O
I
I/O
NAME AND FUNCTION
Digital Power Supply:
+5V power supply pin during normal operation, idle and power-down mode.
Start ADC Operation:
Input starting analog to digital conversion (ADC operation can also be started
by software).
Pulse Width Modulation:
Output 0.
Pulse Width Modulation:
Output 1.
Enable Watchdog Timer:
Enable for T3 watchdog timer and disable power-down mode.
Port 0:
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In this application it uses strong internal
pull-ups when emitting 1s.
Port 1:
8-bit I/O port. Alternate functions include:
(P1.0–P1.7):
Quasi-bidirectional port pins.
CT0I–CT3I (P1.0–P1.3):
Capture timer input signals for timer T2.
T2 (P1.4):
T2 event input
RT2 (P1.5):
T2 timer reset signal. Rising edge triggered.
Port 2:
8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08–A15).
Port 3:
8-bit quasi-bidirectional I/O port. Alternate functions include:
RxD(P3.0):
Serial input port.
TxD (P3.1):
Serial output port.
INT0 (P3.2):
External interrupt.
INT1 (P3.3):
External interrupt.
T0 (P3.4):
Timer 0 external input.
T1 (P3.5):
Timer 1 external input.
WR (P3.6):
External data memory write strobe.
RD (P3.7):
External data memory read strobe.
Port 4:
8-bit quasi-bidirectional I/O port. Alternate functions include:
CMSR0–CMSR5 (P4.0–P4.5):
Timer T2 compare and set/reset outputs on a match with timer T2.
CMT0, CMT1 (P4.6, P4.7):
Timer T2 compare and toggle outputs on a match with timer T2.
Port 5:
8-bit input port.
ADC0–ADC7 (P5.0–P5.7):
Alternate function: Eight input channels to ADC.
Reset:
Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows.
Crystal Input 1:
Input to the inverting amplifier that forms the oscillator, and input to the internal clock
generator. Receives the external clock signal when an external oscillator is used.
Crystal Input 2:
Output of the inverting amplifier that forms the oscillator. Left open–circuit when an
external clock is used.
Digital ground.
Program Store Enable:
Active-low read strobe to external program memory.
Address Latch Enable:
Latches the low byte of the address during accesses to external memory. It is
activated every six oscillator periods. During an external data memory access, one ALE pulse is
skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up.
External Access:
When EA is held at TTL level high, the CPU executes out of the internal program
ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU
executes out of external program memory. EA is not allowed to float.
Analog to Digital Conversion Reference Resistor:
Low-end.
Analog to Digital Conversion Reference Resistor:
High-end.
Analog Ground
Analog Power Supply
P1.0–P1.7
16–23
16–23
16–19
20
21
39–46
24–31
24
25
26
27
28
29
30
31
7–14
7–12
13, 14
68–62,
1
15
35
34
36, 37
47
48
I/O
I/O
I/O
I
I
I/O
I/O
P2.0–P2.7
P3.0–P3.7
P4.0–P4.7
I/O
O
O
I
I/O
I
O
I
O
O
P5.0–P5.7
RST
XTAL1
XTAL2
V
SS
PSEN
ALE
EA
49
I
AV
REF–
AV
REF+
AV
SS
AV
DD
58
59
60
61
I
I
I
I
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V
DD
+0.5V or V
SS
– 0.5V,
respectively.
1992 Jan 08
5
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