Rev 3; 9/06
50MHz to 122.88MHz VCXO
General Description
The DS4077 is an integrated voltage-controlled crystal
oscillator (VCXO) module designed to provide reference
clock generation in base stations, telecom/datacom, and
wireless applications. The DS4077 is developed using a
fundamental quartz crystal plus a unique integrated cir-
cuit design. The internal fundamental quartz crystal
determines the frequency of operation. Custom frequen-
cies are available. Contact the factory for availability.
The DS4077 is designed for use with applications requir-
ing low phase noise and jitter. Jitter performance of bet-
ter than 0.8ps RMS is achieved over the 12kHz to 20MHz
range. Phase noise performance of better than
-125dBc/Hz at 1kHz is achieved with this design.
♦
50MHz to 122.88MHz Frequency
♦
3.135V to 3.465V Operation
♦
Low Jitter: < 0.8ps RMS
♦
±69ppm Absolute Pull Range (APR)
♦
Output Options:
LVCMOS Output Buffer
LVDS Complementary Output Buffer
♦
Minimum ±110ppm Tuning Range (+25°C)
♦
14mm x 9mm x 3.06mm Plastic LGA Package
Features
DS4077
Applications
Clock-Data Recovery in Telecom/Datacom
Applications
Data Retiming
Reference Clock Generation in Base Stations
and Wireless Applications
Ordering Information
PART
DS4077L-DCN
DS4077L-DDN
DS4077L-CCN
DS4077L-CDN
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
OUTPUT TYPE
LVCMOS
LVDS
LVCMOS
LVDS
FREQUENCY
(f
NOM
) (MHz)
54
54
61.44
61.44
PIN-PACKAGE
9 LGA
9 LGA
9 LGA
9 LGA
TOP MARK
DS4077L-DCN
DS4077L-DDN
DS4077L-CCN
DS4077L-CDN
Ordering Information continued at end of data sheet.
Pin Configuration
TOP VIEW
N.C.
9
N.C.
8
N.C.
7
Block Diagram
V
DD
X1
VC 1
N.C. 2
V
SS
3
6
5
4
V
DD
N.C. (LVDSO-)
LVCMOS (LVDSO+)
VC
LVCMOS
OUTPUT
OSC
CRYSTAL
X2
VARACTOR
CONTROL
DS4077
LGA
( ) LVDS OPTION
TRANSFER-MOLDED PLASTIC PACKAGE
LVCMOS OPTION SHOWN HERE.
DS4077
______________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
50MHz to 122.88MHz VCXO
DS4077
ABSOLUTE MAXIMUM RATINGS
VC, V
DD
, LVCMOS, LVDSO+, LVDSO- Output ........-0.3V, +3.6V
Operating Temperature Range
(noncondensing) ..............................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Thermal Resistance
Junction to Ambient .................................................91.06°C/W
Junction to Case ......................................................44.51°C/W
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature
(reflow, 2 passes max)....See IPC/JEDEC STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.135V to 3.465V, T
A
= -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, V
DD
= 3.3V, unless otherwise
noted.) (Note 1)
PARAMETER
V
DD
Operating Supply Range
V
DD
Supply Current
Frequency
Frequency vs. V
DD
Sensitivity
Frequency vs. Load Sensitivity
Frequency vs. Temperature
VC Voltage Range
Frequency Tuning Sensitivity
Tuning Voltage Bandwidth
Absolute Pull Range
VC Input Leakage
Aging, First Year
Aging, Years 0–10
LVDS OUTPUT
Output High Voltage
Output Low Voltage
Differential Output Voltage
Output Common-Mode Variation
Offset Output Voltage
Differential Output Impedeance
Output Current
Output Current
Output Rise Time (Differential)
Output Fall Time (Differential)
V
OHLVDSO
V
OLLVDSO
V
ODLVDSO
V
LVDSOCOM
V
OFFLVDSO
R
OLVDSO
I
VSSLVDSO
I
LVDSO
t
RLVDSO
t
FLVDSO
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
Short ground
Short together (Note 3)
20% to 80% (Note 3)
80% to 20% (Note 3)
150
150
1.125
80
0.925
250
400
150
1.275
140
40
12
1.475
V
V
mV
mV
V
Ω
mA
mA
ps
ps
SYMBOL
V
DD
I
DD
f
OUT
V
DD
ppm
LOADpmm
TEMPppm
VC
RANGE
VC
SEN
VC
BW
f
TUNE
I
LCV
AGEppm
t
AGE
Total aging
(Note 3)
VC = 0.3V to 2.8V (Note 2)
VC = 0V to V
DD
Output open
f
OUT
≤
106.25MHz
f
OUT
> 106.25MHz
VC = 1.6V, V
DD
= 3.3V, T
A
= +25°C
(Note 2)
V
DD
= 3.3V ±5%
10pF to 20pF (Note 3)
From +25°C
-20
0.3
41
10
-69
-500
-5
-10
+69
+500
+5
+10
1.60
f
NOM
–8ppm
-3.5
-1
+20
2.8
164
CONDITIONS
MIN
3.135
TYP
3.3
20
25
f
NOM
MAX
3.465
30
mA
35
f
NOM
+8ppm
+11.5
MHz
ppm
ppm/pF
ppm
V
ppm/V
kHz
ppm
nA
ppm
ppm
UNITS
V
2
_____________________________________________________________________
50MHz to 122.88MHz VCXO
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.135V to 3.465V, T
A
= -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, V
DD
= 3.3V, unless otherwise
noted.) (Note 1)
PARAMETER
LVCMOS OUTPUT
Output Logic 0
Output Logic 1
Output Rise Time
Output Fall Time
Duty Cycle
Harmonics
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
Jitter (12kHz to 20MHz)
LVCMOS
V
OL
V
OH
t
R
t
F
D
CYC
H
Output Current -450µA
Output Current +450µA
Load condition: 10pF to ground; 10% to
90% V
DD
(Note 3)
Load condition: 10pF to ground; 90% to
10% V
DD
(Note 3)
Load condition: 10pF, V
DD
/ 2 (Note 3)
V
DD
= 3.3V, T
A
= +25°C (Note 3)
40
-18
-70
-100
-125
-145
-150
0.8
ps
RMS
dBc/Hz
0
V
DD
-
0.8V
0.4
V
DD
2
2
60
-8
V
V
ns
ns
%
dBc/Hz
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DS4077
SSB PHASE NOISE AND JITTER, V
DD
= 3.3, T
A
= +25°C (Note 3)
Note 1:
Note 2:
Note 3:
Note 4:
Limits at -40°C are guaranteed by design and not production tested.
10pF, LVCMOS.
Guaranteed by design and not production tested.
100Ω differential load.
Pin Description
PIN
LVCMOS
1
2, 5, 7, 8, 9
3
4
6
—
LVDS
1
2, 7, 8, 9
3
—
6
4, 5
NAME
VC
N.C.
V
SS
LVCMOS
V
DD
LVDSO+/LVDSO-
VCXO Control Voltage
No Connection
Ground
LVCMOS Output
DC Power
LVDS Positive and Negative Outputs
FUNCTION
_____________________________________________________________________
3
50MHz to 122.88MHz VCXO
DS4077
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
LVCMOS OUTPUT FREQUENCY
vs. LOAD CAPACITANCE vs. VC
DS4077 toc01
FREQUENCY vs. TEMPERATURE
10
8
6
f
OUT
DEVIATION (ppm)
4
2
0
-2
-4
-6
-8
-10
-40
-20
40
TEMPERATURE (°C)
0
20
60
80
f
OUT
= 77.76MHz
VC = 1.55V
150
125
100
f
OUT
DEVIATION (ppm)
75
50
25
0
-25
-50
-75
-100
-125
0.3
f
OUT
= 77.76MHz
C
L
= 0pF
C
L
= 20pF
0.8
1.3
VC (V)
1.8
2.3
2.8
OUTPUT FREQUENCY
vs. SUPPLY VOLTAGE vs. VC
f
OUT
DEVIATION FROM V
DD
= 3.3V (ppm)
15
10
5
0
-5
VC = 1.6V
-10
-15
-20
3.135 3.190
VC = 2.8V
VC = 0.3V
f
OUT
= 77.76MHz
T
A
= +25°C
DS4077 toc03
20
3.245 3.300 3.355
V
DD
(V)
3.410
3.465
4
_____________________________________________________________________
DS4077 toc02
50MHz to 122.88MHz VCXO
Ordering Information (continued)
PART
DS4077L-ECN
DS4077L-EDN
DS4077L-FCN
DS4077L-FDN
DS4077L-ACN
DS4077L-ADN
DS4077L-0CN
DS4077L-0DN
DS4077L-GCN
DS4077L-GDN
DS4077L-BDN
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
OUTPUT TYPE
LVCMOS
LVDS
LVCMOS
LVDS
LVCMOS
LVDS
LVCMOS
LVDS
LVCMOS
LVDS
LVDS
FREQUENCY
(f
NOM
) (MHz)
74.17582
74.17582
74.25
74.25
76.8
76.8
77.76
77.76
106.25
106.25
122.88
PIN-PACKAGE
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
TOP MARK
DS4077L-ECN
DS4077L-EDN
DS4077L-FCN
DS4077L-FDN
DS4077L-ACN
DS4077L-ADN
DS4077L-0CN
DS4077L-0DN
DS4077L-GCN
DS4077L-GDN
DS4077L-BDN
DS4077
Package Information
For the latest package outline information and land patterns, go to
www.maxim-ic.com/packages.
PACKAGE TYPE
9 LGA
PACKAGE CODE
L949A-1
DOCUMENT NO.
21-0265
Revision History
Rev 0;
Rev 1;
Rev 2;
8/05:
12/05:
6/06:
Initial release.
Added LVDS option.
Changed device description/frequency range; changed jitter typical value from 1 to 0.8psRMS;
added new parts numbers to Ordering Information table; changed jitter range upper limits from
80MHz to 20MHz.
Changed V
DD
ppm units from ppm/PF to ppm; added separate I
DD
parameter for parts with f
OUT
greater than 106.25MHz.
Rev 3;
9/06:
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________
5
© 2006 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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