IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 1-BIT TO 2-BIT
ADDRESS DRIVER WITH
3-STATE OUTPUTS AND
BUS-HOLD
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
μ
• Rail-to-Rail output swing for increased noise margin
• Available in TVSOP package
IDT74ALVCHS162830
DESCRIPTION:
This 1-bit to 2-bit address driver is built using advanced dual metal CMOS
technology. Diodes to V
CC
have been added on the inputs to clamp
overshoot.
The ALVCHS162830 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCHS162830 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
V
CC
OE
2
21
V
CC
OE
1
20
V
CC
A
1
7
5
1
Y
1
4
2
Y
1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4718/3
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
2
Y
2
1
Y
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
Y
3
2
Y
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
GND
2
Y
1
1
Y
1
GND
1
Y
4
2
Y
4
V
CC
A
1
A
2
GND
A
3
A
4
GND
A
5
A
6
V
CC
A
7
A
8
GND
A
9
OE
1
OE
2
A
10
GND
A
11
A
12
V
CC
A
13
A
14
GND
A
15
A
16
GND
A
17
A
18
V
CC
2
Y
18
1
Y
18
V
CC
1
Y
5
2
Y
5
GND
1
Y
6
2
Y
6
GND
1
Y
7
2
Y
7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
V
CC
1
Y
8
2
Y
8
GND
1
Y
9
2
Y
9
1
Y
10
2
Y
10
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
OEx
Ax
xYx
Data Inputs
(1)
3-State Outputs
Description
3-State Output Enable Inputs (Active LOW)
GND
1
Y
11
2
Y
11
V
CC
1
Y
12
2
Y
12
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
GND
1
Y
13
2
Y
13
FUNCTION TABLE
(1)
Inputs
OE
1
L
L
H
H
L
L
H
OE
2
H
H
L
L
L
L
H
Ax
H
L
H
L
H
L
X
1
Yx
Outputs
2
Yx
GND
1
Y
14
2
Y
14
H
L
Z
Z
H
L
Z
Z
Z
H
L
H
L
Z
V
CC
1
Y
15
2
Y
15
GND
2
Y
17
1
Y
17
GND
1
Y
16
2
Y
16
TVSOP
TOP VIEW
2
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
Parameter
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
ΔI
CC
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Driver Outputs enabled
Power Dissipation Capacitance per Driver Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
49
6
V
CC
= 3.3V ± 0.3V
Typical
53
7.5
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK(O)
Parameter
Propagation Delay
Ax to xYx
Output Enable Time
OEx
to xYx
Output Disable Time
OEx
to xYx
Output Skew
(2)
—
—
—
—
—
500
ps
1
4.9
—
5.4
1.7
5.2
ns
1
5.7
—
5.7
1
4.8
ns
Min.
1.2
Max.
3.8
V
CC
= 2.7V
Min.
—
Max.
4
V
CC
= 3.3V ± 0.3V
Min.
1.7
Max.
3.5
Unit
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
V
LOAD/2
OUTPUT
SWITCH
V
T
NORMALLY
CLOSED
LOW
t
PHZ
t
PZH
OUTPUT
SWITCH
NORMALLY
V
T
OPEN
HIGH
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
ALVC Link
V
CC
500Ω
Pulse
Generator
(1, 2)
V
LOAD
Open
GND
V
IN
D.U.T.
R
T
V
OUT
500Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
OUTPUT 2
t
PLH2
t
PHL2
V
T
ALVC Link
Pulse Width
ALVC Link
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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