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IDT72V3611L20PF

Description
3.3 VOLT CMOS SyncFIFO 64 x 36
File Size193KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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IDT72V3611L20PF Overview

3.3 VOLT CMOS SyncFIFO 64 x 36

3.3 VOLT CMOS SyncFIFO
TM
64 x 36
FEATURES:
IDT72V3611
64 x 36 storage capacity
Supports clock frequencies up to 67MHz
Fast access times of 10ns
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (AF) and Almost-Empty (AE) flags
Microprocessor Interface Control Logic
Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
Industrial temperature range (–40°C to +85°C) is available
°
°
Pin and functionally compatible version of the 5V operating
IDT723611
DESCRIPTION:
The IDT72V3611 is a pin and functionally compatible version of the
IDT723611, designed to run off a 3.3V supply for exceptionally low power
consumption. This device is a monolithic, high-speed, low-power, CMOS
Synchronous (clocked) FIFO memory which supports clock frequencies up to
67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO
buffers data from Port A to Port B. The FIFO operates in IDT Standard mode
and has flags to indicate empty and full conditions, and two programmable flags,
Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number
of words is stored in memory. Communication between each port can take place
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Parity
Gen/Check
MBF1
PEFB
PGB
Parity
Generation
Output
Register
RST
ODD/
EVEN
Mail 1
Register
Input
Register
Reset
Logic
RAM
ARRAY
64 x 36
36
36
A
0
- A
35
Write
Pointer
Read
Pointer
B
0
- B
35
EF
AE
FF
AF
FIFO
Status Flag
Logic
Programmable
Flag Offset
Registers
FS
0
FS
1
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4657 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
DSC-4657/1

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