64Kx16 Bit High Speed Static RAM(5.0V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary
2.2. Delete L-version.
2.3. Delete Data Retention Characteristics and Waveform.
2.4. Add Capacitive load of the test environment in A.C test load
2.5. Change D.C characteristics
Previous spec.
Changed spec.
Items
(8/10/12ns part)
(8/10/12ns part)
Icc
200/190/180mA
200/195/190mA
Isb
30mA
50mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Rev. 2.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of th is
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 2.0
February 1998
-1-
KM6161002B, KM6161002BI
64K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50 mA(Max.)
(CMOS) : 10 mA(Max.)
Operating KM6161002B - 8 : 200 mA(Max.)
KM6161002B - 10 : 195 mA(Max.)
KM6161002B - 12 : 190 mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O
1
~ I/O
8,
UB : I/O
9
~ I/O
16
• Standard Pin Configuration
KM6161002BJ : 44-SOJ-400
KM6161002BT : 44-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM6161002B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
KM6161002B uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control ( UB, LB). The device is fabricated
using SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
KM6161002B is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward.
PIN CONFIGURATION
A
0
A
1
A
2
A
3
A
4
CS
1
2
3
4
5
6
7
8
9
(Top View)
44 A
15
43 A
14
42 A
13
41 OE
40 UB
39 LB
38 I/O
16
37 I/O
15
36 I/O
14
ORDERING INFORMATION
KM6161002B -8/10/12
KM6161002BI -8/10/12
Commercial Temp.
Industrial Temp.
I/O
1
I/O
2
I/O
3
I/O
4
10
Vcc 11
Vss 12
I/O
5
13
I/O
6
14
I/O
7
15
I/O
8
16
WE 17
A
5
18
A
6
19
SOJ/
TSOP2
35 I/O
13
34 Vss
33 Vcc
32 I/O
12
31 I/O
11
30 I/O
10
29 I/O
9
28 N.C.
27 A
12
26 A
11
25 A
10
24 A
9
23 N.C.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
I/O
1
~I/O
8
I/O
9
~I/O
16
Pre-Charge Circuit
Row Select
Memory Array
256 Rows
256x16 Columns
A
7
20
A
8
21
N.C. 22
PIN FUNCTION
Data
Cont.
Data
Cont.
Gen.
CLK
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
I/O Circuit &
Column Select
Pin Name
A
0
- A
15
WE
CS
OE
LB
UB
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
1
~I/O
8
)
Upper-byte Control(I/O
9
~I/O
16
)
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
WE
OE
UB
LB
CS
I/O
1
~ I/O
16
V
CC
V
SS
N.C
-2-
Rev 2.0
February 1998
KM6161002B, KM6161002BI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress r ating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5*
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5**
0.8
Unit
V
V
V
V
NOTE: The above parameters are also guaranteed at industrial temperature range.
*
V
IL
(Min) = -2.0V a.c(Pulse Width≤6ns) for I≤20mA
**
V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width≤6ns) for I≤20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
8ns
10ns
12ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1
*
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=-0.1mA
Min
-2
-2
-
-
-
-
-
-
2.4
-
Max
2
2
200
195
190
50
10
0.4
-
3.95
mA
mA
V
V
V
Unit
µA
µA
mA
NOTE: The above parameters are also guaranteed at industrial temperature range.
* V
CC
=5.0V, Temp.=25°C
CAPACITANCE*
(T
A
=25°C , f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
* NOTE : Capacitance is sampled and not 100% tested.
-3-
Rev 2.0
February 1998
KM6161002B, KM6161002BI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
NOTE: The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+5.0V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
480Ω
255Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Symbol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
BHZ
t
OH
KM6161002B-8
Min
8
-
-
-
-
3
0
0
0
0
0
3
Max
-
8
8
4
4
-
-
-
4
4
4
-
KM6161002B-10
Min
10
-
-
-
-
3
0
0
0
0
0
3
Max
-
10
10
5
5
-
-
-
5
5
5
-
KM6161002B-12
Min
12
-
-
-
-
3
0
0
0
0
0
3
Max
-
12
12
6
6
-
-
-
6
6
6
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.0
February 1998
KM6161002B, KM6161002BI
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width( OE High)
Write Pulse Width( OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
BW
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM6161002B-8
Min
8
6
0
6
6
8
6
0
0
4
0
3
Max
-
-
-
-
-
-
-
-
4
-
-
-
KM6161002B-10
Min
10
7
0
7
7
10
7
0
0
5
0
3
Max
-
-
-
-
-
-
-
-
5
-
-
-
CMOS SRAM
KM6161002B-12
Min
12
8
0
8
8
12
8
0
0
6
0
3
Max
-
-
-
-
-
-
-
-
6
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: The above parameters are also guaranteed at industrial temperature range.
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