PIC32MZ2025DAH169T-I-6J datasheet, PDF

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PIC32MZ2025DAH169T-I-6J: Description32-bit Microcontrollers - MCU 32-bit cache-based MCU, Graphics Integrated, stacked DDR2; Categorysemiconductor The embedded processor and controller; File Size10MB，826 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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PIC32MZ2025DAH169T-I-6J Overview

32-bit Microcontrollers - MCU 32-bit cache-based MCU, Graphics Integrated, stacked DDR2

PIC32MZ2025DAH169T-I-6J Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Microchip
Product Category	32-bit Microcontrollers - MCU
Shipping Restrictions	This product may require additional documentation to export from the United States.
RoHS	Details
Packaging	Reel
Factory Pack Quantity	1500

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PIC32MZ Graphics (DA) Family

32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash,

640 KB SRAM, and 32 MB DDR2 SDRAM) with XLP Technology

Operating Conditions

• 2.2V to 3.6V, -40ºC to +85ºC, DC to 200 MHz

• 2.2V to 3.6V, -40ºC to +105ºC (Planned)

Core: 200 MHz / 330 DMIPS MIPS32

microAptiv™

•

32 KB I-Cache, 32 KB D-Cache

MMU for optimum embedded OS execution

microMIPS™ mode for up to 35% smaller code size

DSP-enhanced core:

- Four 64-bit accumulators

- Single-cycle MAC, saturating and fractional math

• Code-efficient (C and Assembly) architecture

Advanced Analog Features

• 12-bit ADC modules:

- 18 Msps with up to six ADC circuits (five dedicated and one

shared)

- Up to 45 analog input

- Can operate during Sleep and Idle modes

- Multiple trigger sources

- Six Digital Comparators and six Digital Filters

• Two Comparators with 32 programmable voltage references

• Temperature sensor with ±2ºC accuracy

• Charge Time Measurement Unit (CTMU)

Clock Management

•

Programmable PLLs and oscillator clock sources

Dedicated PLL for DDR2

Fail-Safe Clock Monitor

Independent Watchdog and Deadman Timers

Fast wake-up and start-up

Communication Interfaces

• Two CAN modules (with dedicated DMA channels):

- 2.0B Active with DeviceNet™ addressing support

• Six UART modules (25 Mbps):

- Supports up to LIN 2.1 and IrDA

protocols

• Six 4-wire SPI modules (up to 50 MHz)

• SQI configurable as additional SPI module (up to 80 MHz)

• Five I

C modules (up to 1 Mbaud) with SMBus support

• Parallel Master Port (PMP)

• Peripheral Pin Select (PPS) to enable function remap

Power Management

• Various power management options for extreme power

reduction (V

BAT

, Deep Sleep, Sleep and Idle)

• Deep Sleep current: < 1 µA (typical)

• Integrated POR and BOR

• Programmable High/Low-Voltage Detect (HLVD) on V

DDIO

and High-Voltage Detect (HVD) on V

DDR1V8

Timers/Output Compare/Input Capture

•

Nine 16-bit and up to four 32-bit timers/counters

Nine Output Compare (OC) modules

Nine Input Capture (IC) modules

Real-Time Clock and Calendar (RTCC) module

5V-tolerant pins with up to 32 mA source/sink

Selectable open drain, pull-ups, and pull-downs

Selectable slew rate control

External interrupts on all I/O pins

PPS to enable function remap

Memory Interfaces

•

DDR2 SDRAM interface (up to DDR2-400)

SD/SDIO/eMMC bus interface (up to 50 MHz)

Serial Quad Interface (up to 80 MHz)

External Bus Interface (up to 50 MHz)

Input/Output

Graphics Features

• 3-layer Graphics Controller with up to 24-bit color support

• High-performance 2D Graphics Processing Unit (GPU)

Audio Interfaces

• Audio data communication: I

S, LJ, and RJ

• Audio control interfaces: SPI and I

• Audio master clock: Fractional clock frequencies with USB

synchronization

Qualification and Class B Support

• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) (Planned)

• Class B Safety Library, IEC 60730

• Back-up internal oscillator

High-Speed Communication Interfaces (with

Dedicated DMA)

• USB 2.0-compliant High-Speed On-The-Go (OTG) controller

• 10/100 Mbps Ethernet MAC with MII and RMII interface

Debugger Development Support

•

In-circuit and in-application programming

4-wire MIPS

Enhanced JTAG interface

Unlimited software and 12 complex breakpoints

IEEE 1149.2-compatible (JTAG) boundary scan

Non-intrusive hardware-based instruction trace

C/C++ compiler with native DSP/fractional support

MPLAB

Harmony Integrated Software Framework

TCP/IP, USB, Graphics, and mTouch™ middleware

MFi, Android™, and Bluetooth

audio frameworks

Security Features

• Crypto Engine with a RNG for data encryption/decryption and

authentication (AES, 3DES, SHA, MD5, and HMAC)

• Advanced memory protection:

- Peripheral and memory region access control

Integrated Software Libraries and Tools

Direct Memory Access (DMA)

• Eight channels with automatic data size detection

• Programmable Cyclic Redundancy Check (CRC)

• RTOS Kernels: Express Logic ThreadX, FreeRTOS™,

OPENRTOS

, Micriµm

µC/OS™, and SEGGER embOS

Packages

Type

Pin Count

I/O Pins (up to)

Contact/Lead Pitch

Dimensions

169

120

0.8 mm

11x11 mm

LFBGA

288

120

0.8 mm

15x15 mm

LQFP

176

120

0.4 mm

20x20 mm



2015-2018 Microchip Technology Inc.

DS60001361G-page 1

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