DATASHEET
DG406, DG407
Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers
The DG406 and DG407 monolithic CMOS analog multiplexers
are drop-in replacements for the popular DG506A and
DG507A series devices. They each include an array of sixteen
analog switches, a TTL and CMOS compatible digital decode
circuit for channel selection, a voltage reference for logic
thresholds, and an ENABLE input for device selection when
several multiplexers are present.
These multiplexers feature lower signal ON-resistance
(<100) and faster transition time (t
TRANS
< 300ns)
compared to the DG506A and DG507A. Charge injection has
been reduced, simplifying sample and hold applications.
The improvements in the DG406 series are made possible by
using a high voltage silicon-gate process. An epitaxial layer
prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30V
P-P
signals when operating with ±15V power
supplies.
The sixteen switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog
signals is quite low over a ±5V analog input range.
FN3116
Rev 11.00
October 1, 2013
Features
• ON-Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
• Low Power Consumption (P
D
) . . . . . . . . . . . . . . . . . . <1.2mW
• Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . . . . 300ns
• Low Charge Injection
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free (RoHS Compliant)
Applications
• Battery Operated Systems
• Data Acquisition
• Medical Instrumentation
• Hi-Rel Systems
• Communication Systems
• Automatic Test Equipment
Related Literature
• Technical Brief
TB363
“Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
80
DG406
MUX
70
r
DS(ON)
, ON-RESISTANCE (W)
60
+85°C
50
+25°C
40
0°C
30
20
10
0
-15
-10
-5
0
5
V
D
, DRAIN VOLTAGE (V)
-40°C
-55°C
V+ = 15V
V- = -15V
10
15
+125°C
BUFFER
ANALOG
INPUTS
ADC
CPU
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. ±15 DUAL SUPPLY r
ON
CURVES AT VARIOUS
TEMPERATURES
FN3116 Rev 11.00
October 1, 2013
Page 1 of 15
DG406, DG407
Pin Configurations
DG406
(28 LD PDIP, SOIC)
TOP VIEW
V+ 1
NC 2
NC 3
S
16
4
S
15
5
S
14
6
S
13
7
S
12
8
S
11
9
S
10
10
S
9
11
GND 12
NC 13
A
3
14
28 D
27 V-
26 S
8
25 S
7
24 S
6
23 S
5
22 S
4
21 S
3
20 S
2
19 S
1
18 EN
17 A
0
16 A
1
15 A
2
DG407
(28 LD PDIP, SOIC)
TOP VIEW
V+ 1
D
B
2
NC 3
S
8B
4
S
7B
5
S
6B
6
S
5B
7
S
4B
8
S
3B
9
S
2B
10
S
1B
11
GND 12
NC 13
NC 14
28 D
A
27 V-
26 S
8A
25 S
7A
24 S
6A
23 S
5A
22 S
4A
21 S
3A
20 S
2A
19 S
1A
18 EN
17 A
0
16 A
1
15 A
2
Pin Description
DG406
(PDIP, SOIC)
1
2, 3, 13
4, 5, 6, 7, 8, 9, 10, 11
12
14, 15, 16, 17
-
18
DG407
(PDIP, SOIC)
1
3, 13, 14,
-
12
-
15, 16, 17
18
SYMBOL
V+
NC
S
16
thru S
9
GND
A
3
thru A
0
A
2
thru A
0
EN
Positive Power Supply
No Connect- No Internal Connection
Source Switch Terminals (These pins can be an input or output)
Ground (0V) Reference
Logic Control Inputs
Logic Control Inputs
Active High Digital Input (When low device is disabled and all switches are
turned off. When high the Ax logic inputs determine which switch is turned
on.
Source Switch Terminals (These pins can be an input or output)
Negative Power Supply (Single supply application this pin will be connected
to ground.)
Drain Switch Terminal (This pin can be an input or output)
Drain Switch Terminal (This pin can be an input or output)
Source Switch Terminals B (These pins can be an input or output)
Source Switch Terminals A (These pins can be an input or output)
DESCRIPTION
19, 20, 21, 22, 23, 24, 25,
26
27
28
-
-
-
-
27
-
2, 28
4, 5, 6, 7, 8, 9, 10, 11
19, 20, 21, 22, 23, 24, 25,
26
S1 thru S8
V
-
D
D
B
, D
A
S
1B
thru S
8B
S
1A
thru S
8A
FN3116 Rev 11.00
October 1, 2013
Page 2 of 15
DG406, DG407
Ordering Information
PART
NUMBER
(Notes 2, 4)
DG406DJZ
DG406DYZ
DG406DYZ-T (Note 1)
DG407DJZ
DG407DYZ
DG407DYZ-T (Note 1)
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
4. For Moisture Sensitivity Level (MSL), please see device information page for
DG406, DG407.
For more information on MSL, please see tech brief
TB363
PART
MARKING
DG406DJZ
DG406DYZ
DG406DYZ
DG407DJZ
DG407DYZ
DG407DYZ
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
28 Ld PDIP (Note 3)
28 Ld SOIC
28 Ld SOIC Tape and Reel
28 Ld PDIP (Note 3)
28 Ld SOIC
28 Ld SOIC Tape and Reel
E28.6
M28.3
M28.3
E28.6
M28.3
M28.3
PKG.
DWG. #
Schematic Diagram
(Typical Channel)
V+
GND
V
REF
D
A
0
V+
A
X
LEVEL
SHIFT
DECODE/
DRIVE
V-
S
1
V+
EN
S
N
V-
FN3116 Rev 11.00
October 1, 2013
Page 3 of 15
DG406, DG407
Functional Diagrams
DG406
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16
D
S
1B
S
2B
S
3B
S
4B
S
5B
S
6B
S
7B
S
8B
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ENABLE
ADDRESS DECODER
1 OF 8
D
B
S
1A
S
2A
S
3A
S
4A
S
5A
S
6A
S
7A
S
8A
D
A
DG407
ENABLE
A
0
A
1
A
2
A
3
EN
A
0
A
1
A
2
EN
Truth Tables
TABLE 1. DG406 TRUTH TABLE
A
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ON SWITCH
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
2
X
0
0
0
0
1
1
1
1
A
1
X
0
0
1
1
0
0
1
1
TABLE 2. DG407 TRUTH TABLE
A
0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
ON SWITCH PAIR
None
1A, 1B
2A, 2B
3A, 3B
4A, 4B
5A, 5B
6A, 6B
7A, 7B
8A, 8B
Logic “0” = V
AL
< 0.8V.
Logic “1” = V
AH
> 2.4V.
X = Don’t Care.
FN3116 Rev 11.00
October 1, 2013
Page 4 of 15
DG406, DG407
Absolute Maximum Ratings
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, V
S
, V
D
(Note 6)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D
(Pulsed 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical, Note 5)
JA
(°C/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. Signals on S
X
, D
X
, EN or A
X
exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, V
AL
= 0.8V, V
AH
= 2.4V Unless Otherwise Specified. Bold-face limits
apply over the operating temperature range, -40°C to +85°C.
PARAMETER
DYNAMIC CHARACTERISTICS
Transition Time, t
TRANS
Break-Before-Make Interval, t
OPEN
Enable Turn-ON Time, t
ON(EN)
Enable Turn-OFF Time, t
OFF(EN)
Charge Injection, Q
OFF-Isolation, OIRR
Logic Input Capacitance, C
IN
Source OFF Capacitance, C
S(OFF)
Drain OFF Capacitance, C
D(OFF)
DG406
DG407
Drain ON Capacitance, C
D(ON)
DG406
DG407
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, V
INH
Logic Low Input Voltage, V
INL
Logic High Input Current, I
AH
Logic Low Input Current, I
AL
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON-Resistance, r
DS(ON)
r
DS(ON)
Matching Between Channels,
r
DS(ON)
V
D
= ±10V, I
S
= +10mA
(Note 9)
V
D
= 10V, -10V (Note 10)
25
Full
25
-
-
-
50
-
5
100
125
-
%
V
A
= 2.4V, 15V
V
EN
= 0V, 2.4V, V
A
= 0V
Full
Full
Full
Full
2.4
-
-1
-1
-
-
-
-
-
0.8
1
1
V
V
µA
µA
V
EN
= 5V, V
D
= 0V, f = 1MHz
25
25
-
-
180
90
-
-
pF
pF
C
L
= 1nF, V
S
= 0V, R
S
= 0
V
EN
= 0V, R
L
= 1k,
f = 100kHz (Note 11)
f = 1MHz
V
EN
= 0V, V
S
= 0V, f = 1MHz
V
EN
= 0V, V
D
= 0V, f = 1MHz
25
25
-
-
160
80
-
-
pF
pF
(See Figure 3)
(See Figure 5)
(See Figure 4)
25
Full
25
Full
25
Full
25
Full
25
25
25
25
-
-
25
10
-
-
-
-
-
-
-
-
200
-
50
-
150
-
70
-
40
-69
7
8
300
400
-
-
200
400
150
300
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
pC
dB
pF
pF
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 12)
TYP
(Note 8)
MAX
(Notes 7, 12)
UNITS
FN3116 Rev 11.00
October 1, 2013
Page 5 of 15
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