INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT368
Hex buffer/line driver; 3-state;
inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state; inverting
FEATURES
•
Inverting outputs
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT368 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT368
The 74HC/HCT368 are hex inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (1OE, 2OE).
A HIGH on nOE causes the outputs to assume a high
impedance OFF-state.
The “368” is identical to the “367” but has inverting outputs.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−1.5
V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
9
3.5
30
HCT
11
3.5
30
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state; inverting
PIN DESCRIPTION
PIN NO.
1, 15
2, 4, 6, 10, 12, 14
3, 5, 7, 9, 11, 13
8
16
SYMBOL
1OE, 2OE
1A to 6A
1Y to 6Y
GND
V
CC
NAME AND FUNCTION
output enable inputs (active LOW)
data inputs
data outputs
ground (0 V)
positive supply voltage
74HC/HCT368
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state; inverting
FUNCTION TABLE
INPUTS
nOE
L
L
H
Note
nA
L
H
X
74HC/HCT368
OUTPUTS
nY
H
L
Z
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state; inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+85
−40
to
+125
max.
145
29
25
225
45
38
225
45
38
90
18
15
ns
74HC/HCT368
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
nA to nY
3-state output enable time
nOE to nY
3-state output disable time
nOE to nY
output transition time
30
11
9
41
15
12
55
20
16
14
5
4
95
19
16
150
30
26
150
30
26
60
12
10
120
24
20
190
38
33
190
38
33
75
15
13
t
PZH
/ t
PZL
ns
Fig.7
t
PHZ
/ t
PLZ
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
December 1990
5
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