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74LVX573M_Q

Description
Latches Octal Latch
Categorysemiconductor    logic   
File Size91KB,7 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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74LVX573M_Q Overview

Latches Octal Latch

74LVX573M_Q Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerON Semiconductor
Product CategoryLatches
RoHSN
Number of Circuits8 Circuit
Logic TypeLatch
Logic Family74L
PolarityNon-Inverting
Quiescent Current4 uA
Number of Output Lines3 Line
High Level Output Current- 4 mA
Propagation Delay Time18 ns at 2.7 V, 12.8 ns at 3.3 V
Supply Voltage - Max3.6 V
Supply Voltage - Min2 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Package / CaseSOIC-20
PackagingTube
FunctionTransparent
Height2.35 mm
Length13 mm
Output Type3-State
TypeD-Type
Width7.6 mm
Mounting StyleSMD/SMT
Number of Channels8 Channels
Number of Input Lines8 Line
Operating Supply Voltage2 V to 3.6 V
Reset TypeNo Reset
Unit Weight0.028254 oz
74LVX573 Low Voltage Octal Latch with 3-STATE Outputs
June 1993
Revised April 2005
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX573M
74LVX573SJ
74LVX573MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
© 2005 Fairchild Semiconductor Corporation
DS011616
www.fairchildsemi.com

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