74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
uc
d
)
ro
(s
P
ct
te
du
le
o
so
Pr
b
e
O
et
) -
ol
(s
bs
ct
O
u
-
od
s)
r
(
P
ct
te
du
le
o
so
Pr
b
e
O
t
le
so
b
O
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 160 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
s)
t(
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHCT74AMTR
74VHCT74ATTR
DESCRIPTION
The 74VHCT74A is an advanced high-speed
CMOS DUAL D-TYPE FLIP FLOP WITH PRESET
AND CLEAR fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
December 2004
Rev. 3
1/14
74VHCT74A
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage (see note 1)
DC Output Voltage (see note 2)
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
uc
d
)
ro
(s
P
ct
te
du
le
o
so
Pr
b
e
O
et
) -
ol
(s
bs
ct
O
u
-
od
s)
r
(
P
ct
te
du
le
o
so
Pr
b
e
O
t
le
so
b
O
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
Parameter
Value
Supply Voltage
Input Voltage
4.5 to 5.5
0 to 5.5
0 to 5.5
Output Voltage (see note 1)
Output Voltage (see note 2)
Operating Temperature
0 to V
CC
0 to 20
T
op
-55 to 125
dt/dv
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
±
0.5V)
1) V
CC
= 0V
2) High or Low State
3) V
IN
from 0.8V to 2V
s)
t(
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) V
CC
= 0V
2) High or Low State
Unit
V
V
V
V
°C
ns/V
3/14
74VHCT74A
Table 8: Capacitive Characteristics
Test Condition
Symbol
Parameter
T
A
= 25°C
Min.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
Typ.
6
21
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per gate)
Figure 4: Test Circuit
uc
d
)
ro
(s
P
ct
te
du
le
o
so
Pr
b
e
O
et
) -
ol
(s
bs
ct
O
u
-
od
s)
r
(
P
ct
te
du
le
o
so
Pr
b
e
O
t
le
so
b
O
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50Ω)
s)
t(
5/14
Embedded System
京公网安备 11010802033920号
EEWORLD
