PMV117EN
µTrenchMOS™
enhanced logic level FET
Rev. 02 — 7 April 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS™ technology.
1.2 Features
s
Logic level threshold
s
Subminiature surface-mounted
package
s
Very fast switching
1.3 Applications
s
Battery management
s
High-speed switch
s
Low power DC-to-DC converter
1.4 Quick reference data
s
V
DS
≤
30 V
s
R
DSon
≤
117 mΩ (V
GS
= 10 V)
s
I
D
≤
2.5 A
s
P
tot
≤
0.83 W
2. Pinning information
Table 1:
Pin
1
2
3
Pinning
Description
gate (G)
source (S)
drain (D)
1
2
3
D
Simplified outline
Symbol
G
SOT23
mbb076
S
Philips Semiconductors
PMV117EN
µTrenchMOS™
enhanced logic level FET
3. Ordering information
Table 2:
Ordering information
Package
Name
PMV117EN
TO-236AB
Description
plastic surface mounted package; 3 leads
Version
SOT23
Type number
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
peak source (diode forward) current T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 10 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−65
−65
-
-
Max
30
30
±20
2.5
1.6
10
0.83
+150
+150
0.8
3.3
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
2 of 12
Philips Semiconductors
PMV117EN
µTrenchMOS™
enhanced logic level FET
120
P
der
(%)
80
03aa17
120
I
der
(%)
80
03aa25
40
40
0
0
50
100
150
T
sp
(
°
C)
200
0
0
50
100
150
T
sp
(
°
C)
200
P
der
P
tot
=
------------------------
×
100
%
P
°
tot
(
25 C
)
V
GS
≥
10 V
I
D
I
der
=
--------------------
×
100
%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature
10
2
I
D
(A)
10
Limit R
DSon
= V
DS
/ I
D
Fig 2. Normalized continuous drain current as a
function of solder point temperature
03ak56
t
p
= 10
µs
100
µs
1
DC
10
−1
1 ms
10 ms
100 ms
10
−2
10
−1
1
10
V
DS
(V)
10
2
T
sp
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
3 of 12
Philips Semiconductors
PMV117EN
µTrenchMOS™
enhanced logic level FET
5. Thermal characteristics
Table 4:
R
th(j-sp)
Thermal characteristics
Conditions
Figure 4
Min
-
Typ
-
Max
100
Unit
K/W
thermal resistance from junction to solder point
Symbol Parameter
10
3
Z
th(j-sp)
(K/W)
10
2
δ
= 0.5
0.2
10
0.1
0.05
0.02
single pulse
1
10
−4
P
03ak55
δ
=
t
p
T
t
p
T
t
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
4 of 12
Philips Semiconductors
PMV117EN
µTrenchMOS™
enhanced logic level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 10
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
and
10
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 24 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 500 mA;
Figure 6
and
8
T
j
= 25
°C
V
GS
= 4.5 V; I
D
= 500 mA;
Figure 6
and
8
T
j
= 25
°C
T
j
= 150
°C
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage
reverse recovery time
I
S
= 0.83 A; V
GS
= 0 V;
Figure 12
I
S
= 1 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V;
V
DS
= 25 V
V
DD
= 15 V; R
L
= 15
Ω;
V
GS
= 10 V
V
GS
= 0 V; V
DS
= 10 V; f = 1 MHz;
Figure 13
I
D
= 0.5 A; V
DD
= 15 V; V
GS
= 10 V;
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
4.6
0.6
1.35
147
65
41
4
7.5
18
13
0.7
69
-
-
-
-
-
-
-
-
-
-
1.2
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
-
-
-
117
188
190
300
mΩ
mΩ
74
117
mΩ
-
-
-
0.01
-
10
0.5
10
100
µA
µA
nA
1.5
1.1
-
2
-
-
-
-
2.7
V
V
V
30
27
37
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
9397 750 14709
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
5 of 12
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