1CY 7C28 7
CY7C287
64K x 8 Reprogrammable Registered PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— t
SA
= 45 ns
•
•
•
•
•
•
•
•
— t
CO
= 15 ns
Low power
— 120 mA
On-chip, edge-triggered output registers
Programmable synchronous or asynchronous output
enable
EPROM technology, 100% programmable
5V
±10%
V
CC
, commercial and military
TTL-compatible I/O
Slim 300-mil package
Capable of withstanding >2001V static discharge
put enable that can be programmed to be synchronous (E
S
) or
asynchronous (E). It is available in a 28-pin, 300-mil package.
The address set-up time is 45 ns and the time from clock HIGH
to output valid is 15 ns.
The CY7C287 is available in a cerDIP package equipped with
an erasure window to provide reprogrammability. When ex-
posed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM float-
ing-gate technology and byte-wide intelligent programming
algorithms.
The CY7C287 offers the advantage of low power, superior per-
formance, and programming yield. The EPROM cell requires
only 12.5V for the supervoltage and low current requirements
allow for gang programming. The EPROM cells allow for each
memory location to be 100% tested with each cell being pro-
grammed, erased, and repeatedly exercised prior to encapsu-
lation. Each PROM is also tested for AC performance to guar-
antee that the product will meet DC and AC specification
limits after customer programming.
Reading the CY7C287 is accomplished by placing an active
LOW signal on E/E
S
. The contents of the memory location
addressed by the address lines (A
0
−
A
15
) will become
available on the output lines (O
0
−
O
7
) on the next rising of
CP.
Functional Description
The CY7C287 is a high-performance 64K x 8 CMOS PROM.
The CY7C287 is equipped with an output register and an out-
Logic Block Diagram
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
E/E
S
CP
OE
REGISTER
PROGRAMMABLE
MULTIPLEXER
C287-1
O
0
COLUMN
ADDRESS
Y
X
ROW
ADDRESS
512x 1024
PROGRAM-
MABLE
ARRAY
8 x 1 of 128
MULTI-
PLEXER
8
SENSE
AMPS
8-BIT
EDGE-
TRIGGERED
REGISTER
O
7
O
6
O
5
O
4
O
3
O
2
O
1
Pin Configurations
CerDIP
Top View
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
28
2
27
3
26
4
25
5
24
6 7C287 23
22
7
21
8
9
20
10
19
11
18
12
17
13
16
14
15
V
CC
A
10
A
11
A
12
A
13
A
14
A
15
CP
E/E
S
O
7
O
6
O
5
O
4
O
3
C287-3
ADDRESS
DECODER
LCC/PLCC
Top View
4 3 2 1 32 31 30
29
5
28
6
7C287
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617 181920
A
5
A
4
A
3
NC
A
2
A
1
A
0
GND
O
0
A
12
A
13
A
14
A
15
NC
CP
E/E
S
O
7
GND
C287-2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose •
CA 95134 •
408-943-2600
September 1994 – Revised December 1994
CY7C287
Selection Guide
7C287−45
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current (mA)
Com’l
Mil
45
15
120
7C287−55
55
20
120
150
7C287−65
65
25
120
150
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................−65
°
C to +150
°
C
Ambient Temperature with
Power Applied..................................................−55
°
C to +125
°
C
Supply Voltage to Ground Potential
.................−0.5V
to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................−0.5V
to +7.0V
DC Input Voltage
.................................................−3.0V
to +7.0V
DC Program Voltage .....................................................13.0V
UV Exposure ................................................ 7258 Wsec/cm
2
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015.2)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
[1]
Military
[2]
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
−55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
7C287−45
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
V
CD
I
OZ
I
OS
I
CC
V
PP
I
PP
V
IHP
V
ILP
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Input Diode Clamp Voltage
Output Leakage Current
Output Short Circuit Current
V
CC
Operating
Supply Current
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming
Voltage
Input LOW Programming
Voltage
3.0
0.4
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
[5]
V
CC
= Max.,
Com’l
I
OUT
= 0 mA
Mil
−40
−20
+40
−90
120
12
13
50
3.0
0.4
12
Test Conditions
V
CC
= Min., I
OH
=
−2.0
mA
V
CC
= Min., I
OL
= 8.0 mA Com’l
Mil
Guaranteed Input Logical HIGH
Voltage for Inputs
Guaranteed Input Logical LOW
Voltage for Inputs
GND < V
IN
< V
CC
−10
2.0
V
CC
0.8
+10
−10
−40
−20
2.0
2.4
0.4
7C287−55
Max.
0.4
0.4
V
CC
0.8
+10
+40
−90
120
150
13
50
3.0
0.4
12
−10
−40
−20
2.0
2.4
7C287−65
Min.
2.4
0.4
0.4
V
CC
0.8
+10
+40
−90
120
150
13
50
V
mA
V
V
V
V
µA
µA
mA
mA
Max. Unit
V
V
Min. Max. Min.
Note 4
Notes:
1. Contact a Cypress representative for industrial temperature range specifications.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See Introduction to CMOS PROMs for general information on testing.
5. Short circuit test should not exceed 30 seconds.
2
CY7C287
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveform
[4]
R1 500Ω
(658Ω MIL)
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
333Ω
(403Ω MIL)
5 pF
R2
333Ω
(403Ω MIL)
C287-6
C287-5
5V
OUTPUT
R1 500Ω
(658Ω MIL)
ALL INPUT PULSES
3.0V
GND
≤
5 ns
90%
10%
90%
10%
≤
5 ns
INCLUDING
JIG AND
C287-4
SCOPE
(a) Normal Load
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
200Ω
(b) High Z Load
2.0V
OUTPUT
250Ω
1.9V
Commercial
Military
C287-7
Switching Characteristics
Over the Operating Range
[3,4]
7C287−45
Parameter
t
SA
t
HA
t
CO
t
HZE
t
DOE
t
PWC
t
SEs[6]
t
HEs[6]
t
HZC[6]
t
COs[6]
Description
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Output Valid
Output High Z from E
Output Valid from E
Clock Pulse Width
E
S
Set-Up to Clock HIGH
E
S
Hold from Clock HIGH
Output High Z from CLK/E
S
Output Valid from CLK/E
S
15
12
5
20
20
Min.
45
0
15
15
15
20
15
8
25
25
Max.
7C287−55
Min.
55
0
20
20
20
25
18
10
30
30
Max.
7C287−65
Min.
65
0
25
25
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
6. Parameters with synchronous E
S
option.
3
CY7C287
Switching Waveform
A
0
−
A
15
t
HA
E
S
t
SEs
t
PWC
CP
t
PWC
t
CO
O
0
−
O
7
VALID
HIGH Z
t
HZE
E
t
DOE
t
HZC
t
COs
t
HEs
t
SEs
t
SA
t
HA
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the CY7C287 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended pe-
riods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV inten-
sity multiplied by exposure time) of 25 Wsec/cm2. For an ultra-
violet lamp with a 12 mW/cm
2
power rating, the exposure time
would be approximately 35 minutes. The CY7C287 needs to
Table 1. CY7C287 Mode Selection
be within 1 inch of the lamp during erasure. Permanent dam-
age may result if the PROM is exposed to high-intensity UV
light for an extended period of time. 7258 Wsec/cm
2
is the
recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be ob-
tained from any Cypress representative.
Pin Function
[7]
Mode: Read or Output Disable
Synchronous Read
Output Disable – Asynchronous
Output Disable – Synchronous
Mode: Other
Program
Program Verify
Program Inhibit
Blank Check
Notes:
7. X = “don’t care” but not to exceed V
CC
±5%.
X can be V
IL
ir V
IH
.
CP
V
IL
/V
IH
X
V
IL
/V
IH
PGM
V
ILP
V
IHP
V
IHP
V
IHP
A
14
A
14
A
14
A
14
LATCH
V
ILP
V
ILP
V
ILP
V
ILP
E, E
S
V
IL
V
IH
V
IH
VFY
V
IHP
V
ILP
V
IHP
V
ILP
A
15
A
15
A
15
A
15
V
PP
V
PP
V
PP
V
PP
V
PP
O
7
−
O
0
O
7
−
O
0
High Z
High Z
D
7
−
D
0
D
7
−
D
0
O
7
−
O
0
High Z
Zeros
4
CY7C287
DIP
LCC
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6 7C287
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
10
A
11
A
12
/A
14
A
13
/A
15
LATCH
V
PP
PGM
VFY
D
7
D
6
D
5
D
4
D
3
C287-9
A
5
A
4
A
3
NC
A
2
A
1
A
0
GND
D
0
4 3 2 1 32 31 30
29
5
28
6
7C287
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14 15 16 17 18 19 20
A
12
/A
14
A
13
/A
15
LATCH
V
PP
NC
PGM
VFY
D
7
GND
C287-10
Figure 1. Programming Pinouts
Architecture Configuration Bits
Architecture
Bit
E/E
S
Device
7C287
D
0
Architecture Verify
D
0
0 = Erased
1 = PGMED
Function
Asynchronous Output Enable (Pin 20 = E)
Synchronous Output Enable (Pin 20 = E
S
)
Bit Map
Programmer Address
(Hex.)
0000
.
.
FFFF
10000
Architecture Byte (10000H
)
D7
D0
C7 C6 C5 C4 C3 C2 C1C0
RAM Data
Data
.
.
Data
Control Byte
5
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