of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
• ISSUE DEFINITION
This issue involves the output buffer entering an unidentified state when the input signals (only Control signals
or Clocks) are floating during reset or initialization of the memory controller after power up.
• PARAMETERS AFFECTED
No timing parameters are affected. The device may drive the outputs even though the read operation is not
enabled. A dummy read is performed to clear this condition.
• TRIGGER CONDITION(S)
Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#)
are floating during reset or initialization of the memory controller after power up.
• SCOPE OF IMPACT
This issue will jeopardize any number of writes or reads which take place after the controls or clock are left
floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to
transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met.
• EXPLANATION OF ISSUE
Figure 3
shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one
of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue
happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into
an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens.
SR LATCH
Figure 3. Output Register Reset Circuit
• WORKAROUND
This is viable only if the customer has the trigger conditions met during reset or initialization of the memory
controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion
of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any
meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly.
“Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The
“dummy” READ can be to any address location in the SRAM. Refer to
Figure 4
for the dummy read implemen-
tation.
Document #: 001-06217 Rev. *C
Page 4 of 8
In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be
performed on every SRAM on the board. Below is an example sequence of events that can be performed
before valid access can be performed on the SRAM.
1) Initialize the Memory Controller
2) Assert RPS# Low for each of the memory devices
Note:
For all devices with x9 bus configuration, the following sequence needs to be performed:
1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummy
read.
2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummy
read.
If the customer has the trigger conditions met during normal access to the memory then there is no workaround
at this point.
K
/K
QDRII Operation
/RPS
Address
A
DataOut (Q)
C
Q(A)
E
Q(A+1)
Q(C)
Q(C+1)
G
Q(E)
Q(E+1)
WE#
Address
DataOut (Q)
Dummy Read
DDRII Operation
A
C
DQ(A)
E
DQ
(A+1)
DQ(C)
DQ
(C+1)
G
DQ
DQ(E)
(E+1)
Figure 4. Dummy Read Implementation
• FIX STATUS
The fix has been implemented on the new revision and is now available. The new revision is an increment of
the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new
revision after the fix.
3. JTAG Mode Issue
• ISSUE DEFINITION
If the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on
this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry
(ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the
ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid
K clock cycles to drive the outputs from high impedance to low impedance levels.
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