Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location speci-
fied on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019BV33 is available in standard 32-pin TSOP
Type II and 400-mil-wide package. The CY7C1018BV33 is
available in a standard 300-mil-wide package.
Functional Description
The CY7C1019BV33/CY7C1018BV33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Logic Block Diagram
Pin Configurations
SOJ / TSOPII
Top View
A
0
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
I/O0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O1
ROW DECODER
I/O2
SENSE AMPS
512 x 256 x 8
ARRAY
I/O3
I/O4
I/O5
I/O6
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O7
Selection Guide
7C1019BV33-10
7C1018BV33-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
L
10
175
5
−
7C1019BV33-12
7C1018BV33-12
12
160
5
0.5
7C1019BV33-15
7C1018BV33-15
15
145
5
0.5
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 11, 2001
CY7C1019BV33
CY7C1018BV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0°C to +70°C
V
CC
3.3V
±
10%
Electrical Characteristics
Over the Operating Range
7C1019BV33-10 7C1019BV33-12 7C1019BV33-15
7C1018BV33-10 7C1018BV33-12 7C1018BV33-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
L
Test Conditions
V
CC
= Min.,
I
OH
= – 4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
175
2.2
–0.3
–1
–5
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
160
2.2
–0.3
–1
–5
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
145
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
20
20
20
mA
I
SB2
5
−
5
0.5
5
0.5
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C1019BV33
CY7C1018BV33
AC Test Loads and Waveforms
R1 480
Ω
R1 480
Ω
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255
Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
Ω
GND
≤
3 ns
3.0V
90%
10%
90%
10%
≤
3 ns
ALL INPUT PULSES
3.3V
OUTPUT
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
1.73V
OUTPUT
Switching Characteristics
[4]
Over the Operating Range
7C1019BV33-10
7C1018BV33-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
10
8
7
0
0
7
5
0
3
5
0
10
12
9
8
0
0
8
6
0
3
6
3
5
0
12
15
10
10
0
0
10
8
0
3
7
0
5
3
6
0
15
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1019BV33-12
7C1018BV33-12
Min.
Max.
7C1019BV33-15
7C1018BV33-15
Min.
Max.
Unit
WRITE CYCLE
[7, 8]
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
3
CY7C1019BV33
CY7C1018BV33
Data Retention Characteristics
Over the Operating Range (L Version Only)
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Conditions
No input may exceed V
CC
+ 0.5V
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Min.
2.0
150
0
200
Max.
Unit
V
µA
ns
µs
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[10, 11]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZCE
DATA VALID
t
PD
50%
ISB
ICC
HIGH
IMPEDANCE
Notes:
9. Device is continuously selected. OE, CE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
4
CY7C1019BV33
CY7C1018BV33
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
[12, 13]
t
WC
ADDRESS
t
SCE
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[12, 13]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 14
t
HZOE
Notes:
12. Data I/O is high impedance if OE = V
IH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
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