QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 997
10/12 BIT 250, 210 AND 170 MSPS ADC
LTC2242-12/10, LTC2241-12/10 OR LTC2240-12/10
DESCRIPTION
Demonstration circuit 997 supports a family of 10/12
BIT 250, 210 and 170 MSPS ADCs. Each assembly fea-
tures one of the following devices: LTC2242-12,
LTC2241-12, LTC2240-12, LTC2242-10, LTC2241-10 or
LTC2240-10 high speed, high dynamic range ADCs.
The versions of the 997B demo board that support the
LTC2242 family of 10 and 12 BIT A/D converters are
listed in Table 1. Depending on the required resolution
and sample rate the DC997 is supplied with the appro-
priate A/D. The circuitry on the analog inputs is opti-
mized for analog input frequencies from 10 MHz to
250 MHz.
Design files for this circuit board are available. Call
the LTC factory.
LTC is a trademark of Linear Technology Corporation
Table 1. DC997B Variants
DC997 VARIANTS
997B-A
997B-B
997B-C
997B-D
997B-E
997B-F
ADC PART NUMBER
LTC2242-12
LTC2241-12
LTC2240-12
LTC2242-10
LTC2241-10
LTC2240-10
RESOLUTION
12-Bit
12-Bit
12-Bit
10-Bit
10-Bit
10-Bit
MAXIMUM SAMPLE
RATE
250Msps
210Msps
170Msps
250Msps
210Msps
170Msps
INPUT FREQUENCY
10MHz < A
IN
< 250MHz
10MHz < A
IN
< 250MHz
10MHz < A
IN
< 250MHz
10MHz < A
IN
< 250MHz
10MHz < A
IN
< 250MHz
10MHz < A
IN
< 250MHz
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 997
10/12 BIT 250, 210 AND 170 MSPS ADC
Table 2. Performance Summary (T
A
= 25°C)
PARAMETER
Supply Voltage
Analog input range
Logic Input Voltages: OE, SHDN
CONDITION
Depending on sampling rate and the A/D converter provided,
this supply must provide up to 500mA.
Depending on Sense Pin Voltage (at converter inputs)
Minimum Logic High
Maximum Logic Low
Logic Output Voltage
(FIN1108T LVDS Buffer)
Sampling Frequency (Convert Clock Frequency)
Encode Clock Level
Resolution
Input frequency range
SFDR
SNR
Minimum Logic High @ -3.4mA w/100Ω Termination
Maximum Logic Low @ +3.4mA w/100Ω Termination
See Table 1
50
Ω
Source Impedance. (Convert Clock input is capacitor cou- 0.2V
P-P
2.5V
P-P
Sine Wave
pled on board and terminated with 50Ω.)
or Square wave
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
VALUE
3.3V ±0.3V (10%); The 2.5V sup-
ply required by the ADC is regulated
locally by U8 from the 3.3V
1V
PP
to 2V
PP
1.7V
0.7V
1.2V +170mV
1.2V – 170mV
QUICK START PROCEDURE
Demonstration circuit 997 is easy to set up to evaluate
the performance of any of the LTC2242 family of High
Speed LVDS output A/D converters - LTC2242-12,
LTC2241-12, LTC2240-12, LTC2242-10, LTC2241-10 or
LTC2240-10. Refer to Figure 1 for proper measure-
ment equipment setup and follow the procedure below:
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 997
10/12 BIT 250, 210 AND 170 MSPS ADC
Sense
Jumpers shown are in the
default positions.
Mode
+3V
-
+
Parallel Data Output
Analog Input
To Data Acquisition Board
OE
Encode Clock
JUMPERS
The DC997 demonstration circuit board should have the
following jumper settings:
JP2 - MODE:
•
•
•
•
VDD: 2’s complement & disable Clock Duty Cy-
cle Stabilizer (Default for LTC2240, 2241)
2/3: 2’s complement & Clock Duty Cycle Stabi-
lizer on (Default for LTC2242)
1/3: Offset Binary & Clock Duty Cycle Stabilizer
on
GND: Offset Binary & Clock Duty Cycle Stabi-
lizer off
SHDN
Figure 1. DC997 Setup
JP3:
•
•
•
•
SHDN & OE GND: Normal operation (Default)
SHDN GND & OE Vdd: Normal operation with high
output impedance
SHDN Vdd & OE GND: Nap Mode with high output
impedance
SHDN Vdd & OE Vdd: Sleep Mode with high output
impedance
JP4 - SENSE:
•
•
Select 2.5V for the 2VPP input range (Default)
Select VCM for the 1VPP input range
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 997
10/12 BIT 250, 210 AND 170 MSPS ADC
POWER
If a DC890B is used to acquire data from the DC997,
the DC890B should be connected to a USB port and
provided an external 6V, 1Amp power supply. The
DC890B will not enable LVDS mode without externally
applied power present. Apply +3.3V across the pins
marked “+3.3V” and “GND” on the DC997. The DC997
demonstration circuit requires up to 500 mA depending
on the sampling rate and the A/D converter supplied.
While the DC890B data collection board is initially pow-
ered by the USB cable, it requires an external power
supply of 6V on the 2.1mm power jack or the adjacent
turrets (+) and (-) before the DC890B will enable LVDS
mode.
ENCODE CLOCK
NOTE: THIS IS NOT A LOGIC LEVEL INPUT.
Apply an
encode clock to the SMA connector on the DC997
demonstration circuit board marked “ENCODE CLK”.
Refer to Table 2 for recommended level, impedance and
coupling. For the best noise performance (SNR AND
SFDR), the ENCODE CLK must be driven with a very
low jitter source. When using a sinusoidal generator,
the amplitude should be large, up to 2.5V
P-P
. Using
bandpass filters on the ENCODE CLK and the Analog
input [AIN] will improve the noise performance by re-
ducing the wideband noise power of the signals. Data
sheet FFT plots are taken with 10 pole LC filters made
by TTE (Los Angeles, CA) to suppress signal generator
harmonics, non-harmonically related spurs and broad
band noise. The very high sampling bandwidth of the
LTC2242 family of parts will fold multiple Nyquist
bands of noise (if present) down to base band raising
the noise floor.
[The LTC2242 family of ADCs provides a flexible En-
code Clock interface capable of accommodating both
single ended and differential sources from LVDS or si-
nusoidal inputs. See the LTC2242 data sheet for other
Encode Clock drive options.]
ANALOG INPUT NETWORK
The input transformer and the RC network on the ana-
log inputs are optimized for 10 to 250MHz. These
components must be optimized for higher or lower in-
put frequencies. Consult the LTC2242 data sheet for
other frequency ranges.
Apply the analog input signal of interest to the SMA
connector on the DC997 demonstration circuit board
marked “AIN”. This input is capacitive coupled to the
input of a MaCom ETC1-1-13 balun or a flux coupled
ETC1-1T transformer. (See Schematic)
DIGITAL OUTPUTS
The LVDS conversion clock output is available on pins
[50, 52] of J2. The LVDS data samples are available on
Pins [8-46, 56-82] for 12 BITS or [8-46, 56-
70] for 10 BITS as LVDS pairs isolated by a ground pin
between each set. The data samples can be collected
via a logic analyzer, cabled to a development system
through a SHORT 100 pin ribbon cable (available from
Samtec - HSC8 series of high speed connectors) or
directly via a DC890B FastDAACS data collection sys-
tem.
SOFTWARE
The DC890B is controlled by the
PScope System Soft-
ware
provided or downloaded from the Linear Technol-
ogy website at
http://www.linear.com/software/.
If a
DC890B was provided, follow the DC890 Quick Start
Guide and the instructions below.
To start the data collection software if “
PScope.exe
”, is
installed (by default) in \Program Files\LTC\PScope\,
double click the PScope Icon or bring up the run win-
dow under the start menu and browse to the PScope
directory and select PScope.
If the DC997 demonstration circuit is properly con-
nected to the DC890, PSCOPE should automatically
detect the DC997, and configure itself accordingly. If
necessary the procedure below explains how to manu-
ally configure PSCOPE.
Under the “Configure” menu, go to “ADC Configura-
tion....” Check the “Config Manually” box and use the
following configuration options, see Figure 2:
Bits: 12 (or 10 for 10 bits parts)
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 997
10/12 BIT 250, 210 AND 170 MSPS ADC
Alignment: 15
FPGA Ld: LVDS
Channs: 1
Bipolar: Checked
Positive-Edge Clk: Unchecked
When evaluating 10 BIT performance using a 12 BIT
part, select the 10 Bit part and PScope will automati-
cally blank the last two LSBs when using a DC997 sup-
plied with a 12 BIT ADC.
If everything is hooked up properly, powered and a
suitable convert clock is present, clicking the “Collect”
button should result in time and frequency plots dis-
played in the PScope window. Additional information
and help for
PScope
is available in the DC890B Quick
Start Guide and in the online help available within the
PScope
program itself.
Figure 2. ADC Configuration
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