VA10800
VA10800
6.4.2
Table of Contents
1
Functional Description
....................... 4
1.1
1.2
1.3
1.4
pins
1.5
1.6
1.7
1.8
Related Documentation
................... 4
Feature Summary
............................. 4
Power-Up Sequence
......................... 8
Power-Up and Reset Behavior of
6.4.3
6.4.4
6.4.5
6.5
Leakage Current non-I2C pads
24
VOL, VOH non-I2C pads
....... 24
I2C Pads
.................................. 25
Input Leakage Current and
Output Voltage I2C Pads
...................... 25
DC Operating Current
Consumption
.............................................. 26
8
Other Resets
..................................... 8
Support for in system programming
I
2
C pins
.............................................. 9
eFuse Writing
................................. 10
6.5.1
6.6
6.7
6.8
Typical Operating Current
Curves
27
DC Standby Current Consumption
28
Internal Weak Pull-up/Pull-down
.. 28
128 pin QFP Pin Capacitance
...... 29
AC Timing Conditions
.................... 30
of the SPI ROM
............................................ 9
2
3
4
Block Diagram
................................. 11
Pin Descriptions
................................ 12
Package Options
............................. 14
4.1
4.2
128 Pin Plastic LQFP
...................... 14
128 Pin Ceramic LQFP
.................. 15
Table of Die Pad Coordinates from
Pad Layout with Marking in Upper
7
AC Electrical Characteristics
........... 30
7.1
7.1.1
loads
7.2
7.3
7.4
7.5
7.6
7.7
Output delay derating for
30
Internal Nominal 1 MHz Oscillator
31
Clock Signal
.................................... 31
GPIO PORTA/PORTB
..................... 31
I
2
C pins
............................................ 32
SPI ROM
.......................................... 35
JTAG
................................................ 37
5
Die Options
...................................... 16
5.1
5.2
Center of Die in Microns
.......................... 16
Left Corner of Die
...................................... 20
7.5.1 I
2
C Pin Timing
............................... 34
6
Ratings Tables
.................................. 21
6.1
6.2
6.3
6.4
Absolute Maximum Ratings
.......... 21
Recommended Supply Operating
Recommended Supply Conditions
21
Signal Pads Operating Conditions
23
8
9
10
Thermal Characteristics
................... 38
Electrostatic Discharge (ESD)
Package Mechanical Information
40
128 Pin Plastic LQFP Nominal
Condition
.................................................... 21
Protection Charcteristics
......................... 39
10.1
6.4.1
Non- I
2
C Pads
.......................... 23
Rev2.1
Package Dimensions (mm)
....................... 40
www.voragotech.com
page 1
VA10800
VA10800
10.2
128 Pin Ceramic LQFP Nominal
Package Dimensions (mm)
....................... 41
11
12
13
14
Ordering Information
.................. 42
Development kit Ordering
Errata
............................................. 43
Revision History
............................ 44
9.1 Part Marking
....................................... 42
Information
.............................................. 42
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Rev2.1
page 2
VA10800
VA10800
Features
§
§
Performance
o
50MHz ARM
®
Cortex
®
-M0 processor
On-Chip Memory
o
32KB Data
o
128KB Program
o
1Kb Efuse memory
56 General Purpose I/O (GPIO) pins
o
Configurable direction
o
Configurable weak pull-up/down
resistors
o
Configurable as edge or level
sensitive interrupt sources
24 General purpose counter/timers
o
Configurable interrupt sources
o
Can be triggered from 2 sources
(GPIO or other counter/timers)
2 UARTS
o
Internal FIFO
o
Transmit or receive interrupt source
2
½
Serial Peripheral Interface (SPI)
ports
o
Internal FIFO
o
Transmit or receive interrupt source
o
Multiple chip select outputs
o
Two ports Master/Slave, one port
Master only
2
2 I C ports
o
Internal FIFO
o
Master and Slave mode on both
ports
o
Standard and Fast mode support
3.3V I/O Supply; 1.5V Core Supply
Description
The VA10800 ARM
®
Cortex
®
-M0
microcontroller chips using
HARDSlL
®
technology are designed for high reliability
applications. They have been designed for
extreme environment applications capable
of operating at extremely high and low
temperatures (-55˚C to 200˚C). These
devices are Latch up immune to the
extreme temperature specification of
200˚C.
The VA10800 is optimized for high
temperature environments and uses lower
power flip-flop storage elements.
§
§
§
§
§
§
www.voragotech.com
Rev2.1
page 3
VA10800
VA10800
1 Functional Description
The VA10800 ARM
®
Cortex
®
-M0 microcontroller chip is designed for extreme temperature
applications. It is capable of operating at extremely high and low temperatures (-55˚C to
200˚C) and within extreme radiation environments. Lower power flip-flop storage elements
have been used in the design to optimize power consumption.
1.1 Related Documentation
The followed related documents will be helpful to fully understand this device:
•
ARM
®
Documents (Available from http://infocenter.arm.com)
o
o
o
o
•
Cortex
®
-M0 Generic User Guide
Cortex
®
-M0 Technical Reference Manual
AMBA
®
3 AHB-Lite Protocol Specification
AMBA
®
3 APB Protocol Specification
NXP Documents (Available from http://www.nxp.com)
o
I
2
C-bus specification and user manual
•
VORAGO Documents
o
VA10800/VA10820 Programmers Guide (Available at
http://voragotech.com)
1.2 Feature Summary
•
Processor Core
o
ARM
®
Cortex
®
-M0 processor
§
§
§
o
o
§
§
§
§
Up to 50 MHz
SysTick Counter
Single Cycle Multiply
32 Interrupts
4 Breakpoint Comparators
2 Data Watch Point Comparators
JTAG Debug Port
Rev2.1
page 4
ARM
®
Cortex
®
-M0 built-in Nested Vectored Interrupt Controller (NVIC)
CoreSight™ compliant debug access via JTAG based Debug interface
www.voragotech.com
VA10800
VA10800
•
Memory
o
o
32kB Data Memory
128kB Code Memory
§
§
•
Peripherals
o
2 UARTs
§
§
16 word Transmit and Receive FIFOs
Fractional baud rate generation
•
§
§
§
§
§
Supports baud rates up to 115200 with system clocks above
2MHz
Supports 5, 6, 7, 8 and 9 bits
Supports Even, Odd, and None parity
Stop Bits 1 or 2
Supports Break generation and detection
Error detection
•
•
•
•
§
•
•
•
o
2
½
SPI Ports
§
§
§
§
§
§
§
Supports all 4 modes of Motorola’s SPI Specification
Word/Frame size of 4 to 16 bits
16 word Transmit and Receive FIFOs
Block mode support for larger Frame sizes
Master mode rates up to 1/4 the system clock
Slave mode rates up to 1/12 the system clock
Configurable Interrupt generation
•
•
FIFO level (fully configurable)
FIFO Overflow
FIFO overflow
Framing error
Parity error
Break detection
FIFO level (fully configurable)
Receive Timeout
Error
Loaded from external Serial Peripheral Interface (SPI) based memory at
startup
Configurable boot delay, boot speed, and boot checking
Configurable Interrupt generation
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Rev2.1
page 5
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