FEDR44V100A-01
Issue Date: Sep. 04, 2017
MR44V100A
1M Bit(131,072-Word -Word
×
8-Bit) FeRAM (Ferroelectric Random Access Memory)
I2C
GENERAL DESCRIPTION
The MR44V100A is a nonvolatile 131,072-word x 8-bit ferroelectric random access memory (FeRAM)
developed in the ferroelectric process and silicon-gate CMOS technology. The MR44V100A is accessed using
Two-wire Serial Interface ( I2C BUS ).Unlike SRAMs, this device, whose cells are nonvolatile, eliminates
battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells
and blocks, such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read
cycle time and the power consumption during a write can be reduced significantly.
The MR44V100A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 10
12
cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 131,072-word
×
8-bit configuration I2C BUS Interface
• A single 3.3 V typ. (1.8V to 3.6V) power supply
• Operating frequency:
3.4MHz(Max) HS-mode
1MHz(Max) F/S-mode Plus
• Read/write tolerance
10
12
cycles/bit
• Data retention
10 years
• Guaranteed operating temperature range
−40
to 85°C
• Low power consumption
Power supply current (@3.4MHz)
1.1mA(Max.)
Standby mode supply current
10μA(Typ.),
50μA(Max.)
Sleep mode supply current
0.1μA(Typ.),
2μA(Max.)
• Package options:
8-pin plastic SOP (P-SOP8-200-1.27-T2K)
• RoHS (Restriction of hazardous substances) compliant
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FEDR44V100A-01
MR44V100A
PIN CONFIGURATION
8-pin plastic SOP
NC
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
MR44V100A
PIN DESCRIPTIONS
Pin Name
NC
Not Connected Pin (open)
It should always be left open or connected to any potential (ground, power supply)
Address ( input )
Address pin indicates device address. When Address value is match the device address
code from SDA, the device will be selected. The address pins are pulled down internally.
Serial data input serial data output ( input / output )
SDA
SDA is a bi-directional line for I2C interface. The output driver is open-drain. A pull-up
resistor is required.
Serial Clock ( input )
SCL
Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on
the rising edge and outputs occur on the falling edge.
Write protect ( input )
WP
Write Protect pin controls write-operation to the memory. When WP is high, all address in
the memory will be protected. When WP is low, all address in the memory will be written.
WP pin is pulled down internally.
Power supply
Apply the specified voltage to V
CC
. Connect V
SS
to ground.
Description
A1 – A2
V
CC
, V
SS
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FEDR44V100A-01
MR44V100A
I2C BUS
The MR44V100A employs a bi-directional two-wire I2C BUS interface, works as a slave device.
An example of I2C interface system with MR44V100A
SCL
SDA
SCL SDA
SCL SDA
SCL SDA
Pull-up
resistor
I2C BUS
MR44V100A
MR44V100A
master
(slave)
A2 A1
(slave)
A2 A1
00
01
I2C BUS COMUNICATION
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always
8bit long, acknowledge is always required after each byte. I2C BUS carries out data transmission with plural
devices connected by 2 communication lines of serial data ( SDA ) and serial clock ( SCL ).
SCL
SDA
1-7
8
9
1-7
8
9
1-7
8
9
ADDRESS
START
condition
R/W
ACK
DATA
ACK
DATA
ACK
STOP
condition
START CONDITION
Before executing each command, start condition ( start bit ) where SDA goes from “HIGH” down to “LOW”
when SCL is “HIGH” is necessary. MR44V100A always detects whether SDA and SCL are in start condition
( start bit ) or not, therefore, unless this condition is satisfied, any command is not executed.
STOP CONDITION
Each command can be ended by SDA rising from “LOW” to “HIGH” when stop condition ( stop bit ), namely,
SCL is “HIGH”.
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FEDR44V100A-01
MR44V100A
ACKNOWLEDGE ( ACK ) SIGNAL
This acknowledge ( ACK ) signal is a software rule to show whether data transfer has been made normally or not.
In master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at
data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
The device (this IC at slave address input of write command, read command, and
μ-COM
at data output of read
command) at the receiver (receiving) side sets SDA “LOW” during 9 clock cycles, and outputs acknowledge
signal ( ACK signal) showing that it has received the 8bit data.
This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( ACK signal)
“LOW”.
Each write action outputs acknowledge signal ( ACK signal ) “LOW”, at receiving 8bit data ( word address and
write data ).
Each read action outputs 8bit data ( read data ), and detects acknowledge signal ( ACK signal ) “LOW”.
When acknowledge signal ( ACK signal ) is detect, and stop condition is not sent from the master (μ-COM) side,
this IC continues data output. When acknowledge signal ( ACK signal ) is not detected, this IC stops data
transfer, and recognizes stop condition ( stop bit ), and ends read action. And this IC gets in status.
SLAVE ADDRESS
Output a slave address after start condition from master.
The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed
to “1010”.
Next slave addresses (A2 A1 … device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses, and next comes most significant bit (WA16).
The most insignificant bit (R/W…READ/WRITE) of slave address is used for designating write or read action,
and is as shown below.
Setting R/W to 0
Setting R/W to 1
write (setting 0 to word address setting of random read)
read
SCL
SDA
START
condition
1
2
3
4
5
6
7
8
9
1
2
1
0
1
0
A2
A1
WA16
R/W
ACK
WRITE PROTECT
When WP terminal is set Vcc(H level), data rewrite of all addresses is prohibited. When it is set Vss(L level),
data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or Vss, or control it to H level or L
level. Because this terminal is pulled down internally, in the case of Open the terminal will be recognized as L
level
During write cycle WP terminal must be always “L” level. WP terminal must be fixed from start condition to
stop condition.
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FEDR44V100A-01
MR44V100A
COMMAND
BYTE WRITE CYCLE
Arbitrary data is written to FeRAM. When to write only 1 byte, byte write is normally used.
start condition
slave address with LSB is 0 (write)
1
st
and 2
nd
word address
byte of write data.
stop condition
S
T
A
R
T
Slave address
1 0 1 0 A2 A1
W
A
16
W
R
I
T
E
1
st
WORD address
W
A
15
A
C
K
W
A
8
A
C
K
2
nd
WORD address
W
A
7
W
A
0
A
C
K
D
7
Write data
D
0
A
C
K
S
T
O
P
PAGE WRITE CYCLE
When to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The
address reaches the final address, the address will be rolled over to the first address. By page write cycle, up to
128K bytes data can be written. When data above the maximum bytes are sent, data from the first byte will be
overwritten.
S
T
A
R
T
Slave address
1 0 1 0 A2 A1
W
A
16
W
R
I
T
E
1 WORD address
W
A
15
A
C
K
W
A
8
A
C
K
st
2
W
A
7
nd
WORD address
W
A
0
A
C
K
D
7
Write data
D
0
A
C
K
D
7
Write data
D
0
A
C
K
S
T
O
P
RANDOM READ CYCLE
Random read cycle is a command to read data by designating address.
Random read sequence
1.
2.
3.
Next to Start condition,
slave address with LSB is 0 (write)
1
st
and 2
nd
word address
Next to Start condition,
slave address with LSB is 1 (read)
The bit of equivalent to WA16 is ignored.
4.
5.
read out byte of data.
ACK to “H”
W
R
I
T
E
W
A
16
A
C
K
S
T
A
R
T
W
A
0
A
C
K
R
E
A
D
D
7
A
C
K
S
T
O
P
D
0
N
A
C
K
6.
Send Stop condition and finish the sequence.
S
T
A
R
T
Slave address
1 0 1 0 A2 A1
1
st
WORD address
W
A
15
W
A
8
A
C
K
2
nd
WORD address
W
A
7
Slave address
1 0 1 0 A2 A1 X
Read data
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