CS5322
Two−Phase Buck Controller
with Integrated Gate
Drivers and 5−Bit DAC
The CS5322 is a two−phase step down controller which
incorporates all control functions required to power high performance
processors and high current power supplies. Proprietary multi−phase
architecture guarantees balanced load current distribution and reduces
overall solution cost in high current applications. Enhanced V
2
™
control architecture provides the fastest possible transient response,
excellent overall regulation, and ease of use.
The CS5322 multi−phase architecture reduces output voltage and
input current ripple, allowing for a significant reduction in inductor
values and a corresponding increase in inductor current slew rate. This
approach allows a considerable reduction in input and output capacitor
requirements, as well as reducing overall solution size and cost.
Features
•
Enhanced V
2
Control Method
•
5−Bit DAC with 1.0% Accuracy
•
Adjustable Output Voltage Positioning
•
4 On−Board Gate Drivers
•
200 kHz to 800 kHz Operation Set by Resistor
•
Current Sensed through Buck Inductors, Sense Resistors, or V−S
Control
•
Hiccup Mode Current Limit
•
Individual Current Limits for Each Phase
•
On−Board Current Sense Amplifiers
•
3.3 V, 1.0 mA Reference Output
•
5.0 V and/or 12 V Operation
•
On/Off Control (through Soft Start Pin)
•
Power Good Output with Internal Delay
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1
SO−28L
DW SUFFIX
CASE 751F
PIN CONNECTIONS AND
MARKING DIAGRAM
COMP
V
FB
V
DRP
CS1
CS2
CS
REF
PWRGD
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
I
LIM
REF
A
WL, L
YY, Y
WW, W
1
28
R
OSC
V
CCL
V
CCL1
GATE(L)1
GND
GATE(H)1
V
CCH1
LGND
SS
V
CCL2
GATE(L)2
GND2
GATE(H)2
V
CCH2
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
CS5322GDW28
CS5322GDWR28
Package
SO−28L
SO−28L
Shipping
27 Units/Rail
1000 Tape & Reel
AWLYYWW
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 7
1
Publication Order Number:
CS5322/D
CS5322
CS5322
+12 V
+5.0 V
1.0
μF
ENABLE
61.9 k
COMP
V
FB
V
DRP
CS1
CS2
CS
REF
PWRGD
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
I
LIM
REF
R
OSC
V
CCL
V
CCL1
GATE(L)1
GND1
GATE(H)1
V
CCH1
LGND
SS
V
CCL2
GATE(L)2
GND2
GATE(H)2
V
CCH2
+
8
×
4SP820M
V
OUT
12
×10 μF
0.1
μF
1.0
μF
1.0
μF
300 nH
+
3
×
16SP270M
600 nH
1.0 nF
4.12 k
34.8 k
12.7 k
PWRGD
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
1.0 k
25.5 k
.01
μF
.01
μF
25.5 k
.01
μF
2.80 k
0.1
μF
1.0
μF
600 nH
1.0 nF
Figure 1. Application Diagram, 12 V to 1.6 V, 35 A Converter
CS5322
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2
CS5322
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature
Lead Temperature Soldering:
Storage Temperature Range
ESD Susceptibility (Human Body Model)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Reflow: (SMD styles only) (Note 1)
Value
150
230 peak
−65
to +150
2.0
Unit
°C
°C
°C
kV
ABSOLUTE MAXIMUM RATINGS
Pin Name
Power for Logic
Power for GATE(L)1
Power for GATE(L)2
Power GATE(H)1
Power for GATE(H)2
Power Good Output
Soft Start Capacitor
Voltage Feedback Compensation
Network
Voltage Feedback Input
Output for Adjusting Adaptive
Voltage Position
Frequency Resistor
Reference Output
High−Side FET Drivers
Pin Symbol
V
CCL
V
CCL1
V
CCL2
V
CCH1
V
CCH2
PWRGD
SS
COMP
V
FB
V
DRP
R
OSC
REF
GATE(H)1−2
V
MAX
16 V
16 V
16 V
20 V
20 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
20 V
V
MIN
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V DC
−2.0
V for 100
ns
−0.3
V DC
−2.0
V for 100
ns
N/A
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
I
SOURCE
N/A
N/A
N/A
N/A
N/A
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.5 A, 1.0
μs
200 mA DC
1.5 A, 1.0
μs
200 mA DC
50 mA
2.0 A, 1.0
μs
200 mA DC
2.0 A, 1.0
μs
200 mA DC
1.0 mA
1.0 mA
1.0 mA
1.0 mA
I
SINK
50 mA
1.5 A, 1.0
μs
200 mA DC
1.5 A, 1.0
μs
200 mA DC
1.5 A, 1.0
μs
200 mA DC
1.5 A, 1.0
μs
200 mA DC
20 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
50 mA
1.5 A, 1.0
μs
200 mA DC
1.5 A, 1.0
μs
200 mA DC
N/A
N/A
N/A
1.0 mA
1.0 mA
1.0 mA
1.0 mA
Low−Side FET Drivers
GATE(L)1−2
16 V
Return for Logic
Return for #1 Driver
Return for #2 Driver
Current Sense for Phases 1−2
Current Limit Set Point
Current Sense Reference
Voltage ID DAC Inputs
LGND
GND1
GND2
CS1−CS2
I
LIM
CS
REF
V
ID0−4
N/A
0.3 V
0.3 V
6.0 V
6.0 V
6.0 V
6.0 V
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CS5322
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< 70°C; 0°C < T
J
< 125°C; 4.7 V < V
CCL
< 14 V; 8.0 V < V
CCH
< 20 V;
C
GATE(H)
= 3.3 nF, C
GATE(L)
= 3.3 nF, R
R(OSC)
= 32.4 k, C
COMP
= 1.0 nF, C
SS
= 0.1
μF,
C
REF
= 0.1
μF,
DAC Code 10000, C
VCC
= 1.0
μF,
I
LIM
≥
1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Voltage Identification DAC (0 = Connected to V
SS
; 1 = Open or Pull−up to 3.3 V)
Accuracy (all codes)
V
ID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
ID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
V
ID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
V
ID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
V
ID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
−
1.064
1.089
1.114
1.139
1.163
1.188
1.213
1.238
1.262
1.287
1.312
1.337
1.361
1.386
1.411
1.436
1.460
1.485
1.510
1.535
1.559
1.584
1.609
1.634
1.658
1.683
1.708
1.733
1.757
1.782
1.807
1.832
1.00
25
3.15
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.25
50
3.30
1.086
1.111
1.136
1.162
1.187
1.212
1.237
1.263
1.288
1.313
1.338
1.364
1.389
1.414
1.439
1.465
1.490
1.515
1.540
1.566
1.591
1.616
1.641
1.667
1.692
1.717
1.742
1.768
1.793
1.818
1.843
1.869
1.50
100
3.45
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
kΩ
V
Measure V
FB
= COMP
±
1.0
%
Input Threshold
Input Pull−up Resistance
Pull−up Voltage
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CS5322
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< 70°C; 0°C < T
J
< 125°C; 4.7 V < V
CCL
< 14 V; 8.0 V < V
CCH
< 20 V;
C
GATE(H)
= 3.3 nF, C
GATE(L)
= 3.3 nF, R
R(OSC)
= 32.4 k, C
COMP
= 1.0 nF, C
SS
= 0.1
μF,
C
REF
= 0.1
μF,
DAC Code 10000, C
VCC
= 1.0
μF,
I
LIM
≥
1.0 V; unless otherwise specified.)
Characteristic
Power Good Output
Power Good Fault Delay
Output Low Voltage
Output Leakage Current
Lower Threshold
Upper Threshold
Voltage Feedback Error Amplifier
V
FB
Bias Current (Note 2)
COMP Source Current
1.0 V < V
FB
< 1.9 V
COMP = 0.5 V to 2.0 V;
V
FB
= 1.8 V; DAC = 00000
COMP = 0.5 V to 2.0 V;
V
FB
= 1.9 V; DAC = 00000
V
FB
= 1.8 V COMP Open; DAC = 00000
V
FB
= 1.9 V COMP Open; DAC = 00000
−10
μA
< I
COMP
< +10
μA
−
Note 3
0.01
μF
COMP Capacitor
−
9.0
15
10.3
30
11.5
60
μA
μA
CS
REF
= V
DAC
to V
DAC
±
15%
CS
REF
= 1.0 V, I
PWRGD
= 4.0 mA
CS
REF
= 1.45 V, PWRGD = 5.5 V
% of Nominal VID Code
% of Nominal VID Code
25
−
−
−14
8
50
0.25
0.1
−11
11
125
0.40
10
−8.0
14
μs
V
μA
%
%
Test Conditions
Min
Typ
Max
Unit
COMP Sink Current
15
30
60
μA
COMP Max Voltage
COMP Min Voltage
Transconductance
Output Impedance
Open Loop DC Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
Soft Start
Soft Start Charge Current
Soft Start Discharge Current
Hiccup Mode Charge/Discharge Ratio
Peak Soft Start Charge Voltage
Soft Start Discharge Threshold Voltage
PWM Comparators
Minimum Pulse Width
2.4
−
−
−
60
−
−
2.7
0.1
32
2.5
90
400
70
−
0.2
−
−
−
−
−
V
V
mmho
MΩ
dB
kHz
dB
0.2 V
≤
SS
≤
3.0 V
0.2 V
≤
SS
≤
3.0 V
−
−
−
15
4.0
3.0
3.3
0.20
30
7.5
4.0
4.0
0.27
50
13
−
4.2
0.34
μA
μA
−
V
V
Measured from CSx to GATE(H)
X
V(V
FB
) = V(CS
REF
) = 1.0 V, V(COMP) = 1.5 V
60 mV step applied between V
CSX
and V
CREF
V(CS1) = V(CS2) = V(V
FB
) = V(CS
REF
) = 0 V;
Measure V(COMP) when GATE(H)1,
GATE(H)2, switch high
−
350
515
ns
Channel Start Up Offset
0.3
0.4
0.5
V
GATE(H) and GATE(L)
High Voltage (AC)
Low Voltage (AC)
Rise Time GATE(H)
X
Rise Time GATE(L)
X
Note 3 Measure V
CCLX
−
GATE(L)
X
or
V
CCHX
−
GATE(H)
X
Note 3 Measure GATE(L)
X or
GATE(H)
X
1.0 V < GATE < 8.0 V; V
CCHX
= 10 V
1.0 V < GATE < 8.0 V; V
CCLX
= 10 V
−
−
−
−
0
0
35
35
1.0
0.5
80
80
V
V
ns
ns
2. The V
FB
Bias Current changes with the value of R
OSC
per Figure 4.
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