CS5157
CPU 5−Bit Synchronous
Buck Controller
The CS5157 is a 5−bit synchronous dual N−Channel buck
controller. It is designed to provide unprecedented transient response
for today’s demanding high−density, high−speed logic. The regulator
operates using a proprietary control method, which allows a 100 ns
response time to load transients. The CS5157 is designed to operate
over a 4.25−16 V range (V
CC
) using 12 V to power the IC and 5.0 V as
the main supply for conversion.
The CS5157 is specifically designed to power Pentium® II
processors and other high performance core logic. It includes the
following features: on board, 5−bit DAC, short circuit protection,
1.0% output tolerance, V
CC
monitor, and programmable Soft Start
capability. The CS5157 is available in 16 pin surface mount.
Features
•
Dual N−Channel Design
•
Excess of 1.0 MHz Operation
•
100 ns Transient Response
•
5−Bit DAC
•
30 ns Gate Rise/Fall Times
•
1.0% DAC Accuracy
•
5.0 V & 12 V Operation
•
Remote Sense
•
Programmable Soft Start
•
Lossless Short Circuit Protection
•
V
CC
Monitor
•
25 ns FET Nonoverlap Time
•
V
2
™
Control Topology
•
Current Sharing
•
Overvoltage Protection
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MARKING
DIAGRAM
16
16
CS5157
AWLYWW
1
1
SOIC−16
D SUFFIX
CASE 751B
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
V
ID0
V
ID1
V
ID2
V
ID3
SS
V
ID4
C
OFF
V
FFB
1
16
V
FB
COMP
LGND
V
CC1
V
GATE(L)
PGND
V
GATE(H)
V
CC2
ORDERING INFORMATION
Device
CS5157GD16
CS5157GDR16
Package
SO−16
SO−16
Shipping
48 Units/Rail
2500 Tape & Reel
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 7
1
Publication Order Number:
CS5157/D
CS5157
12 V
5.0 V
0.1
μF
V
CC1
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
330 pF
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
C
OFF
SS
COMP
LGND
V
GATE(L)
IRL3103
V
CC2
IRL3103
2.0
μH
1200
μF/10
V
×
3
AIEI
V
GATE(H)
1.3 V to 3.5 V @ 13 A
CS5157
PGND
0.1
μF
V
FB
3.3 k
V
FFB
100 pF
0.33
μF
1200
μF/10
V
×
5
AIEI
Figure 1. Application Diagram, Switching Power Supply for Core Logic
−
Pentium
)
II Processor
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature, T
J
Lead Temperature Soldering:
Storage Temperature Range, T
S
ESD Susceptibility (Human Body Model)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Reflow: (SMD styles only) (Note 1)
Value
0 to 150
230 peak
−65
to +150
2.0
Unit
°C
°C
°C
kV
ABSOLUTE MAXIMUM RATINGS
Pin Name
V
CC1
V
CC2
SS
COMP
V
FB
C
OFF
V
FFB
V
ID0
−
V
ID4
V
GATE(H)
V
GATE(L)
LGND
PGND
Max Operating Voltage
16 V/−0.3 V
16 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
16 V/−0.3 V
16 V/−0.3 V
0V
0V
Max Current
25 mA DC/1.5 A peak
20 mA DC/1.5 A peak
−100
μA
200
μA
−0.2
μA
−0.2
μA
−0.2
μA
−50
μA
100 mA DC/1.5 A peak
100 mA DC/1.5 A peak
25 mA
100 mA DC/1.5 A peak
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2
CS5157
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8.0 V < V
CC1
< 14 V; 5.0 V < V
CC2
< 14 V;DAC
Code: V
ID4
= V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
and CV
GATE(H)
= 1.0 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless otherwise specified.)
Characteristic
Error Amplifier
V
FB
Bias Current
Open Loop Gain
Unity Gain Bandwidth
COMP SINK Current
COMP SOURCE Current
COMP CLAMP Current
COMP High Voltage
COMP Low Voltage
PSRR
V
CC1
Monitor
Start Threshold
Stop Threshold
Hysteresis
V
GATE(H)
and V
GATE(L)
Out SOURCE Sat at 100 mA
Out SINK Sat at 100 mA
Out Rise Time
Out Fall Time
Delay V
GATE(H)
to V
GATE(L)
Delay V
GATE(L)
to V
GATE(H)
V
GATE(H)
, V
GATE(L)
Resistance
V
GATE(H)
, V
GATE(L)
Schottky
Soft Start (SS)
Charge Time
Pulse Period
Duty Cycle
COMP Clamp Voltage
V
FFB
SS Fault Disable
High Threshold
PWM Comparator
Transient Response
V
FFB
Bias Current
V
FFB
= 0 to 5.0 V to V
GATE(H)
= 9.0 V to 1.0 V;
V
CC1
= V
CC2
= 12 V
V
FFB
= 0 V
−
−
100
0.3
125
−
ns
μA
−
−
(Charge Time /Pulse Period)
×
100
V
FB
= 0 V; V
SS
= 0
V
GATE(H)
= Low; V
GATE(L)
= Low
−
1.6
25
1.0
0.50
0.9
−
3.3
100
3.3
0.95
1.0
2.5
5.0
200
6.0
1.10
1.1
3.0
ms
ms
%
V
V
V
Measure V
CC1
−
V
GATE(L)
; V
CC2
−
V
GATE(H)
Measure V
GATE(H)
−
V
PGND
; V
GATE(L)
−
V
PGND
1.0 V < V
GATE(H)
< 9.0 V; 1.0 V < V
GATE(L)
< 9.0 V;
V
CC1
= V
CC2
= 12 V
9.0 V > V
GATE(H)
> 1.0 V; 9.0 V > V
GATE(L)
> 1.0 V;
V
CC1
= V
CC2
= 12 V
V
GATE(H)
falling to 2.0 V; V
CC1
= V
CC2
= 8.0 V;
V
GATE(L)
rising to 2.0 V
V
GATE(L)
falling to 2.0 V; V
CC1
= V
CC2
= 8.0 V;
V
GATE(H)
rising to 2.0 V
Resistor to LGND
LGND to V
GATE(H)
@ 10 mA
LGND to V
GATE(L)
@ 10 mA
−
−
−
−
−
−
20
−
1.2
1.0
30
30
25
25
50
600
2.0
1.5
50
50
50
50
100
800
V
V
ns
ns
ns
ns
kΩ
mV
Output switching
Output not switching
Start−Stop
3.75
3.70
−
3.90
3.85
50
4.05
4.00
−
V
V
mV
V
FB
= 0 V
1.25 V < V
COMP
< 4.0 V; Note 2
Note 2
V
COMP
= 1.5 V; V
FB
= 3.0 V; V
SS
> 2.0 V
V
COMP
= 1.2 V; V
FB
= 2.7 V; V
SS
= 5.0 V
V
COMP
= 0 V; V
FB
= 2.7 V
V
FB
= 2.7 V; V
SS
= 5.0 V
V
FB
= 3.0 V
8.0 V < V
CC1
< 14 V @ 1.0 kHz; Note 2
−
50
500
0.4
30
0.4
4.0
−
60
0.3
60
3000
2.5
50
1.0
4.3
160
85
1.0
−
−
8.0
70
1.6
5.0
600
−
μA
dB
kHz
mA
μA
mA
V
mV
dB
Test Conditions
Min
Typ
Max
Unit
2. Guaranteed by design, not 100% tested in production.
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3
CS5157
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8.0 V < V
CC1
< 14 V; 5.0 V < V
CC2
< 14 V;DAC
Code: V
ID4
= V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
and CV
GATE(H)
= 1.0 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless otherwise specified.)
Characteristic
DAC
Input Threshold
Input Pull Up Resistance
Pull Up Voltage
Accuracy
V
ID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
ID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
V
ID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
V
ID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
V
ID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1.2870
1.3365
1.3860
1.4355
1.4850
1.5345
1.5840
1.6335
1.6830
1.7325
1.7820
1.8315
1.8810
1.9305
1.9800
2.0295
1.2315
2.0790
2.1780
2.2770
2.3760
2.4750
2.5740
2.6730
2.7720
2.8710
2.9700
3.0690
3.1680
3.2670
3.3660
3.4650
1.3000
1.3500
1.4000
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
1.2440
2.1000
2.2000
2.3000
2.4000
2.5000
2.6000
2.7000
2.8000
2.9000
3.0000
3.1000
3.2000
3.3000
3.4000
3.5000
1.3130
1.3635
1.4140
1.4645
1.5150
1.5655
1.6160
1.6665
1.7170
1.7675
1.8180
1.8685
1.9190
1.9695
2.0200
2.0705
1.2564
2.1210
2.2220
2.3230
2.4240
2.5250
2.6260
2.7270
2.8280
2.9290
3.0300
3.1310
3.2320
3.3330
3.4340
3.5350
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ID0,
V
ID1
, V
ID2
, V
ID3
, V
ID4
V
ID0,
V
ID1
, V
ID2
, V
ID3
, V
ID4
−
Measure V
FB
= V
COMP
, 25°C
≤
T
J
≤
85°C
1.00
25
4.85
−
1.25
50
5.00
−
2.40
100
5.15
1.0
V
kΩ
V
%
Test Conditions
Min
Typ
Max
Unit
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4
CS5157
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8.0 V < V
CC1
< 14 V; 5.0 V < V
CC2
< 14 V;DAC
Code: V
ID4
= V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
and CV
GATE(H)
= 1.0 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless otherwise specified.)
Characteristic
Supply Current
I
CC1
I
CC2
Operating I
CC1
Operating I
CC2
C
OFF
Normal Charge Time
Extension Charge Time
Discharge Current
Time Out Timer
Time Out Time
Fault Mode Duty Cycle
V
FB
= V
COMP
; V
FFB
= 2.0 V;
Record V
GATE(H)
Pulse High Duration
V
FFB
= 0V
10
35
30
50
50
65
μs
%
V
FFB
= 1.5 V; V
SS
= 5.0 V
V
SS
= V
FFB
= 0
C
OFF
to 5.0 V; V
FB
> 1.0 V
1.0
5.0
5.0
1.6
8.0
−
2.2
11.0
−
μs
μs
mA
No Switching
No Switching
V
FB
= COMP = V
FFB
V
FB
= COMP = V
FFB
−
−
−
−
8.5
1.6
8.0
2.0
13.5
3.0
13
5.0
mA
mA
mA
mA
Test Conditions
Min
Typ
Max
Unit
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−16
1, 2, 3, 4, 6
PIN SYMBOL
V
ID0
−V
ID4
FUNCTION
Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic
ones if left open. V
ID4
selects the DAC range. When V
ID4
is High (logic one), the DAC
range is 2.10 V to 3.50 V with 100 mV increments. When V
ID4
is Low (logic zero), the
DAC range is 1.30 V to 2.05 V with 50 mV increments. V
ID0
−
V
ID4
select the desired
DAC output voltage. Leaving all 5 DAC input pins open results in a DAC output voltage
of 1.2440 V, allowing for adjustable output voltage, using a traditional resistor divider.
Soft Start Pin. A capacitor from this pin to LGND in conjunction with internal 60
μA
cur-
rent source provides Soft Start function for the controller. This pin disables fault detect
function during Soft Start. When a fault is detected, the Soft Start capacitor is slowly dis-
charged by internal 2.0
μA
current source setting the time out before trying to restart the
IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator
output is shorted.
A capacitor from this pin to ground sets the time duration for the on board one shot,
which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is connected to the regulator
output. The inner feedback loop terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents
V
GATE(H)
and V
GATE(L)
from being in high state simultaneously.
High current ground for the IC. The MOSFET driver is referenced to this pin. Input capac-
itor ground and the source of lower FET should be tied to this pin.
Low FET driver pin capable of 1.5 A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be provided externally to
compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage feedback which sets the
output voltage. This pin can be connected directly to the output or a remote sense trace.
5
SS
7
8
9
10
11
12
13
14
15
16
C
OFF
V
FFB
V
CC2
V
GATE(H)
PGND
V
GATE(L)
V
CC1
LGND
COMP
V
FB
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