2305-1HDCGI8 datasheet, PDF - EEWORLD Datasheet

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2305-1HDCGI8: DescriptionSOIC-8, Reel; Categorylogic logic; File Size283KB，13 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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2305-1HDCGI8 Overview

SOIC-8, Reel

2305-1HDCGI8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Manufacturer packaging code	DCG8
Reach Compliance Code	compli
ECCN code	EAR99
series	2305
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e3
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
propagation delay (tpd)	0.35 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
minfmax	133 MHz
Base Number Matches	1

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IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

3.3V ZERO DELAY

CLOCK BUFFER

IDT2305

FEATURES:

•

Phase-Lock Loop Clock Distribution

10MHz to 133MHz operating frequency

Distributes one clock input to one bank of five outputs

Zero Input-Output Delay

Output Skew < 250ps

Low jitter <200 ps cycle-to-cycle

IDT2305-1 for Standard Drive

IDT2305-1H for High Drive

No external RC network required

Operates at 3.3V V

Power down mode

Available in SOIC/TSSOP packages

DESCRIPTION:

The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one

reference input, and drives out five low skew clocks. The -1H version of this

device operates, up to 133MHz frequency and has a higher drive than the

-1 device. All parts have on-chip PLLs which lock to an input clock on the

REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT

pad. In the absence of an input clock, the IDT2305 enters power down. In

this mode, the device will draw less than 25

µA,

the outputs are tri-stated,

and the PLL is not running, resulting in a significant reduction of power.

The IDT2305 is characterized for both Industrial and Commercial

operation.

FUNCTIONAL BLOCK DIAGRAM

CLKOUT

PLL

REF

Control

Logic

CLK1

CLK2

CLK3

CLK4

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2012

Integrated Device Technology, Inc.

AUGUST 2012

DSC 5174/8

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