PFM19030
SPECIFICATION
1930-1990 MHz, 30W, 2-Stage Power Module
Enhancement-Mode Lateral MOSFETs
This versatile PCS module provides excellent linearity and efficiency in a
low-cost surface mount package. The PFM19030 includes two stages of
Package Type: Surface Mount
amplification, along with internal sense FETs that are on the same silicon
PN: PFM19030SM
die as the RF devices. These thermally coupled sense FETs simplify the
task of bias temperature compensation of the overall amplifier. The module
includes RF input, interstage, and output matching elements. The source
and load impedances required for optimum operation of the module are
much higher (and simpler to realize) than for unmatched Si LDMOS
transistors of similar performance.
The surface mount package base is typically soldered to a conventional
PCB pad with an array of via holes for grounding and thermal sinking
of the module. Optimized internal construction supports low FET
channel temperature for reliable operation.
Package Type: Flange
PN: PFM19030F
•
28 dB Gain
•
30 Watts Peak Output Power
•
Internal Sense FETs
(for improved bias control)
•
IS95 CDMA Performance
5 Watts Average Output Level
20% Power Added Efficiency
–49 dBc ACPR
Module Schematic Diagram
Module Substrate
Q1 Die Carrier
Q1
Q2 Die Carrier
Q2
Drain 2
RF OUT
Output
Match
Lead
Gate 1
RF IN
Lead
Input
Match
Output
Match
Input
Match
S1
S2
Sense S1
Gate 2
Lead
Lead
Sense S2
Lead
D1
Lead
Note: Additionally, there are 250 KOhm resistors connected in shunt with all leads, to enhance ESD protection.
Page 1 of 15
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
PFM19030
Electrical Specification
Parameter
Min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Operating Frequency
Gain
Gain Compression at
Pout =30 Watts
Gain Flatness over any
30 MHz bandwidth
Deviation from Linear
Phase over any 30
MHz bandwidth
Group Delay
ACPR with IS95A
CDMA Pave = 5 W
Efficiency under IS-95
Protocol, Pave = 5 W
Efficiency @ 30W
CW Output
DC Drain Supply
Voltage
Operating
Temperature Range
(base temperature)
Gain Variation versus
Temperature
Output Mismatch
Stress
Stability
Theta jc (channel)
Quiescent Currents
a) Q1
b) Q2
Sense FET Current/RF
FET Current Ratio
a) Stg 1 Sense
b) Stg 2 Sense
ESD Protection
a) Human Body Model
b) Machine Model
1930
27.0
-
-
-
-
-45
18
Limits
Typ
-
29.0
0.8
±
0.2
±
0.8
3.1
-49
20.5
42
Units
Max
1990
31.5
1.5
±
0.3
±
1.5
3.7
-
-
-
30
+115
-
30
-
2.1
MHz
dB
dB
dB
°
nanosec
dBc
%
%
Volts
°C
dB/°C
Watts
CW
dBc
°C/W
mA
mA
Note 1.
Comments
Pulsed CW compression measurement
(12
µsec
pulse, 120
µsec
period, 10%
duty cycle).
Includes delay of test fixture (~0.6
nanosec.).
Note 3. Refer to applications data for
performance with other protocols.
Note 3.
24
-40
-
-
-60
-
27
-
-0.033
-
-
1.9
75
260
Testing for conformance with RF
specifications is at +27 V.
Testing for conformance with RF
specification is at +25
°C.
Bias quiescent currents held constant.
VSWR 10:1, all phase angles. No
degradation in output power before &
after test.
0<Pout<44.8 dBm CW, 3:1 VSWR
Theta jc is for output device. Verified
with IR scan. Note 2.
These DC quiescent currents are typical
of the levels that produce optimum
linearity for CDMA protocol.
Ratio of sense FET current, relative to RF
FET current. Ratios are: Stg 1: 33:1;
Stg 2: 58:1 Gates of sense & RF FETs
are DC connected. Measured with no RF
signal present.
a) 2000V, 100 pF, 1500 Ohms
b) 400V, 200 pF, zero Ohms
Mil STD 883E, Method 3015 for Human
Body Model and for Machine Model.
17
3.0
1.7
%
%
18
Class 1
Class M3
Page 2 of 15
Specifications subject to change without notice. US Patent No.6,822,321
http://www.cree.com/
Rev. 2
PFM19030
Electrical Specification (Continued)
MAXIMUM RATINGS
Rating
19
DC Drain Supply
a) Drain-to-Source Voltage, (V
GS
=0), D1 & D2
& Track D1 & Track D2
b) Normal Operation (Class AB operation)
DC Gate Supply
a) Gate-to-source Voltage (V
DS
=0)
Normal Operation (Class AB operation)
RF Input Power
Maximum Power Dissipation (T
≤
+85
°C)
a) Derate above +85
°C
base temperature.
Maximum Channel Operating Temperature
Storage Temperature Range
Symbol
V
DS
V
D_SUPPLY
V
GS
V
G_SUPPLY
P
IN
P
TOTAL
T
CH
T
STG
Value
+50
+30
-0.5<V
GS
<+15
0<V
GS
<+6
+25
65
-0.7
+200
-40 to +150
Units
Volts DC
Volts DC
Volts DC
Volts DC
dBm
Watts
Watts/°C
°C
°C
20
21
22
23
24
RECOMMENDED SOURCE AND LOAD IMPEDANCES
Impedance
Nominal Source
Impedance for
Optimum Operation
Nominal Load
Impedance for
Optimum Operation
19 + j1.9
Units
Ohms
Comments
Matched for near-optimum linearity and gain flatness.
Impedance is looking from the module input lead into the
input matching circuit. Reference plane is 0.105 inches from
the input end (case edge)of the module.
Matched for near-optimum linearity under CDMA protocol.
Impedance is from the module output lead looking into the
output matching circuit. Reference plane is 0.105 inches from
the output end (case edge) of the module.
21 + j6.3
Ohms
Specification Notes:
1) The module is mounted in a test fixture with external matching elements for all testing. Quiescent current bias
conditions are those appropriate for minimum ACPR under CDMA protocol. Supply voltage for all tests is
+27 volts DC. Testing is at +25
°C
unless otherwise specified.
2) Theta jc is measured with a package mounting (base) temp of +85
°C,
and with 10 Watts CW output.
3) Pout=5Watts average; IS-95A protocol: IS95 Forward Link PPS+ 9CH.
ACPR conditions: a) 900 kHz offset, 30 kHz BW, b) 2.75 MHz offset, 1 MHz BW.
4) Sense FETs are scaled versions of the main RF FETs, formed from electrically isolated cells at end of the RF
structure. Current scales according to periphery (threshold voltages offset is less than
±150
millivolts between
adjacent devices). RF & Sense FET gates and sources are DC connected. Drains are DC isolated. Leads S1 & S2
are DC connected to drains of sense FETs 1 & 2. Sources are connected to package base. Sense FETs are
electrically isolated from the RF signals.
Page 3 of 15
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
PFM19030
Typical Module Performance
T=+25
°C,
unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Typical Small-Signal Gain vs. Frequency
31
30
Gain (dB)
29
28
27
Gain & Efficiency vs. Output Power
Pulsed Measurement, Vdc=+27V, F=1960 MHz
29
28
Gain (dB)
27
26
25
60%
50%
40%
30%
20%
10%
30
32
34
36
38
40
42
44
46
Ouptput Power (dBm)
Efficiency
26
1840
1870
1900
1930
1960
1990
2020
2050
2080
24
Frequency (MHz)
Input and Output Return Loss vs Frequency.
0
Typical Output Power at 1 dB Gain
Compression vs Freq. & Supply Voltage
47
Output Power (dBm)
46
45
44
43
1870
1900
1930
1960
1990
Frequency (MHz)
2020
2050
P1dB(+26V)
P1dB(+27V)
P1dB(+28V)
-2
Return Loss (dB)
-4
-6
-8
-10
-12
-14
1900
1930
1960
Frequency (MHz)
1990
2020
INPUT
OUTPUT
Typical S21 Phase Variation Versus Frequency
(normalized about average insertion phase)
3
Typical CW Gain vs Swept CW Output Power,
with Various Quiescent Bias Conditions
30
29
Bias for Best 2-Tone
IMDs
2
Phase (degrees)
0
-1
-2
Gain (dB)
1
28
27
26
25
G(75/250 mA)
G(68/225 mA)
G(60/200 mA)
G(82/275 mA)
-3
1930
1945
1960
Frequency (MHz)
1975
1990
24
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
CW Swept Output Power (dBm)
T
i m
e
d
e l a y
o
f f s e t
=
3
. 2
n
a n
o
s e c
( i n
c l u
d
e s
t i m
e
d
e l a y
o
f
t e s t
f i x
t u
r e ) .
Note: This data illustrates the significance of quiescent bias
current level. The unit was press mounted in the fixture &
thermal effects are exagerated for this CW test.
Page 4 of 15
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
PFM19030
Typical Module Performance
Typical CW 2-Tone Intermods vs. Output Power
Intermodulation Distortion (dBc)
-10
-20
-30
-40
-50
-60
-70
30
31
32
33
34 35 36 37 38 39 40
Average Output Power (dBm)
41
42
43
IM3L
IM3U
IM5L
IM5U
IM7L
IM7U
T=+25
°C,
unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Single-Signal IS95 CDMA ACPR & Efficiency
vs Average Output Power (F=1960 MHz)
-20
-25
-30
ACPR (dBc)
-35
-40
-45
-50
-55
-60
-65
-70
30
F1=1959.5 MHz, F2=1960.5 MHz
Vsupply = +27 V, Idsq1 = 75 mA, Idsq2=250 mA
ACPR(-900 KHz)
ACPR(+900 KHz)
ACPR(-1.25 MHz)
ACPR(+1.25 MHz)
ACPR(-2.75 MHz)
ACPR(+2.75 MHz)
PAE (%)
30
27
24
18
15
12
9
6
3
0
Efficiency (%)
21
31
32
33
34
35
36
37
38
Average CDMA Output Power (dBm)
39
2-Tone IMD Rejection vs. Tone Separation
(Peak Envelope Power = 44.5 dBm)
0
IM Rejection (dBc)
-10
-20
-30
-40
-50
-60
0
10
20
30
40
50
CW Tone Separation (MHz)
IM3L
IM3U
IM5L
IM5U
IM7L
IM7U
2 IS95 CDMA Signal IM Distortion
vs. Ave Output Power (F=1955, 1965 MHz)
-20
-25
IM Rejection (dBc)
-30
-35
-40
-45
-50
-55
-60
30
31
32
33
34
35
36
CDMA Total Average Power (dBm)
37
38
IM3(+15 MHz)
IM3(-15 MHz)
IM5(-25 MHz)
IM5(+25 MHz)
F1=1930 MHz, F2=1930.5 MHz to 1980 MHz
Vsupply = +27 V, Idsq1 = 75 mA, Idsq2=250 mA
WCDMA ACLR & Efficiency vs Output
Power (F=1960 MHz, Test Model 1)
-15
-20
-25
ACLR (dBc)
-30
-35
-40
-45
-50
30
31
32
33
34
35
36
37
38
Average WCDMA Output Power (dBm)
39
ACLR(-5 MHz)
ACLR (+5 MHz)
Efficiency
28
24
Efficiency (%)
20
16
12
8
4
0
Page 5 of 15
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
Microcontroller MCU
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