EEWORLDEEWORLDEEWORLD

Part Number

Search

54121-810041500LF

Description
Power to the Board Unshrouded vertical stacked header, Through Hole, Single Row, 4 Positions, 2.54mm (0.100in) Pitch.
CategoryThe connector   
File Size90KB,1 Pages
ManufacturerFCI / Amphenol
Download Datasheet Parametric View All

54121-810041500LF Online Shopping

Suppliers Part Number Price MOQ In stock  
54121-810041500LF - - View Buy Now

54121-810041500LF Overview

Power to the Board Unshrouded vertical stacked header, Through Hole, Single Row, 4 Positions, 2.54mm (0.100in) Pitch.

54121-810041500LF Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerFCI / Amphenol
Product CategoryPower to the Board
PDS: Rev :L
STATUS:Released
Printed: Dec 24, 2014
STM8 UART problem
After the STM8's UART is initialized, data cannot be sent. Only after adding this function at the end of the routine can it be sent. I would like to ask the masters if there is any other operation req...
stonepal stm32/stm8
How to divide and connect analog ground and digital ground?
After reading some articles, I still have some questions about analog and digital ground. Please give me more advice. 1. The requirement of single-point grounding is to make single-point grounding at ...
mwl0223 Analog electronics
【GD32F350 Sharing】Simple Pedometer Design
[i=s]This post was last edited by hanyeguxingwo on 2018-9-22 13:57[/i] [align=center][color=#333333][font=Tahoma][b][size=4]Simple pedometer design[/size][/b][/font][/color][/align] [align=left][b][Po...
hanyeguxingwo GD32 MCU
Help with ARM300 issues
I encountered a very simple problem when doing a course project... But I couldn't solve it... My source code is as follows/*****************************************************************************...
eestudent ARM Technology
The vivado simulation output waveform signal input is all Z and the output is all X
Source file: `timescale 1ns / 1ps module clk_counter(inputsys_clk,inputrst_n,inputgate,output reg[31:0]clk_cnt,output regcounter_valid);always@(posedge sys_clk or negedge rst_n)beginif(rst_n == 1'b0)b...
1nnocent FPGA/CPLD
Embedded development direction
Hello everyone, I am a student who is about to graduate and study embedded. So far, I still have doubts about the future development of embedded. In the domestic and international conferences over the...
花心大萝卜 Talking about work

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 844  1350  46  683  63  17  28  1  14  2 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号