SI5347A-B04229-GMR datasheet, PDF

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SI5347A-B04229-GMR: DescriptionClock Synthesizer / Jitter Cleaner Low-Jitter, Quad DSPLL, 8-Output, Any Frequency (<712.5MHz), Any Output, Jitter Attenuator; Categorysemiconductor Analog mixed-signal IC; File Size997KB，55 Pages; ManufacturerSilicon Laboratories

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SI5347A-B04229-GMR Overview

Clock Synthesizer / Jitter Cleaner Low-Jitter, Quad DSPLL, 8-Output, Any Frequency (<712.5MHz), Any Output, Jitter Attenuator

SI5347A-B04229-GMR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Clock Synthesizer / Jitter Cleaner
Packaging	Box

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Si5347/46 Rev D Data Sheet

Dual/Quad DSPLL

™

Any-Frequency, Any-Output Jitter

Attenuators

The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates

four any-frequency DSPLLs for applications that require maximum integration and inde-

pendent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each

DSPLL has access to any of the four inputs and can provide low jitter clocks on any of

the device outputs. Based on 4

generation DSPLL technology, these devices provide

any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL

supports independent free-run, holdover modes of operation, as well as automatic and

hitless input clock switching. The Si5347/46 is programmable via a serial interface with

in-circuit programmable non-volatile memory so that it always powers up in a known

configuration. Programming the Si5347/46 is easy with Silicon Labs'

ClockBuilder Pro

software. Factory pre-programmed devices are also available.

KEY FEATURES

• Four or two independent DSPLLs, any

output frequency from any input frequency

• Ultra-low jitter of 95 fs rms

• Input frequency range:

• External Crystal: 25–54 MHz

• Differential: 8 kHz to 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range:

• Differential: up to 712.5 MHz

• LVCMOS: up to 250 MHz

• Status Monitoring

• Hitless switching

• Si5347: 4 input, 8 output, 64-QFN 9×9 mm

• Si5346: 4 input, 4 output, 44-QFN 7×7 mm

Applications

• OTN Muxponders and Transponders

• 10/40/100G network line cards

• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)

• Carrier Ethernet switches

• Broadcast video

25-54 MHz XTAL

OSC

IN0

4 Input

Clocks

IN1

IN2

IN3

÷FRAC

DSPLL A

DSPLL B

DSPLL C

DSPLL D

÷INT

Status Flags

I2C / SPI

Status Monitor

Control

NVM

OUT0

Si5346A/B

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Si5347A/B

Si5347C/D

silabs.com

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Rev. 1.0

Si5347/46 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5347 takes advantage of Silicon Labs’ 4

generation DSPLL technology to offer the industry’s most integrated and flexible jitter

attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common

serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. Any of the

output clocks (OUT0 to OUT7) can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller

form factor dual DSPLL version with four inputs and four outputs.

3.1 Frequency Configuration

The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile

memory. The combination of fractional input dividers (P

), fractional frequency multiplication (M

), and integer output division

) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a spe-

cific frequency plan are easily determined using the ClockBuilder Pro utility.

3.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth set-

tings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,

each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.

3.2.1 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting

a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-

ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock

acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting, as described in

Section

3.2 DSPLL Loop Bandwidth.

The fastlock feature can be enabled or disabled independently for each of the DSPLLs.

3.3 Modes of Operation

Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition

Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in

Figure 3.1 Modes of Operation

on page 4.

The following sections describe each of these modes in greater detail.

3.3.1 Initialization and Reset

Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard

reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-

stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register

reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all

DSPLLs, while a soft reset can either affect all or each DSPLL individually.

silabs.com

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Rev. 1.0 | 3

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