LPC804
32-bit Arm
®
Cortex
®
-M0+ microcontroller; up to 32 KB flash
and 4 KB SRAM; 12-bit ADC; Comparator; 10-bit DAC;
Capacitive Touch Interface; Programmable Logic Unit
Rev. 1.4 — 12 July 2018
Product data sheet
1. General description
The LPC804 are an Arm
Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU
frequencies of up to 15 MHz. The LPC804 supports 32 KB of flash memory and 4 KB of
SRAM.
The peripheral complement of the LPC804 includes a CRC engine, two I
2
C-bus
interfaces, up to two USARTs, one SPI interface, Capacitive Touch Interface (Cap Touch),
one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one
12-bit ADC, one 10-bit DAC, one analog comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, Programmable Logic Unit (PLU),
and up to 30 general-purpose I/O pins.
For additional documentation related to the LPC804 parts, see
Section 19.
2. Features and benefits
System:
Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz
with single-cycle multiplier and fast single-cycle I/O port.
Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
AHB multilayer matrix.
Serial Wire Debug (SWD) with four break points and two watch points. JTAG
boundary scan (BSDL) supported.
Memory:
Up to 32 KB on-chip EEPROM based flash programming memory.
Code Read Protection (CRP).
4 KB SRAM.
Dual I/O power (LPC804M111JDH24):
Independent supplies on each package side permitting level-shifting signals from
one off-chip voltage domain to another and/or interfacing directly to off-chip
peripherals operating at different supply levels.
The switch matrix provides level shifter functionality to allow up to two selected
signals to be routed from user-selected pins in one voltage domain to selected pins
in the alternate domain. This feature can also be used on a single supply device if
voltage level shifting is not required.
ROM API support:
Boot loader.
NXP Semiconductors
LPC804
32-bit Arm Cortex-M0+ microcontroller
Supports Flash In-Application Programming (IAP).
Supports In-System Programming (ISP) through USART.
On-chip ROM APIs for integer divide.
Free Running Oscillator (FRO) API.
Digital peripherals:
High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 30
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, and input inverter. GPIO direction control
supports independent set/clear/toggle of individual bits.
High-current source output driver (20 mA) on five pins.
GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
Switch matrix for flexible configuration of each I/O pin function.
CRC engine.
Capacitive Touch Interface.
Programmable Logic Unit (PLU) to create small combinatorial and/or sequential
logic networks including simple state machines.
Timers:
One 32-bit general purpose counter/timer, with four match outputs and three
capture inputs. Supports PWM mode, and external count
Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to
four programmable, fixed rates.
Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a
low-power, low-frequency internal oscillator, or an external clock input.
Windowed Watchdog timer (WWDT).
Analog peripherals:
One 12-bit ADC with up to 12 input channels with multiple internal and external
trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports
two independent conversion sequences.
Comparator with five input pins and external or internal reference voltage.
One 10-bit DAC.
Serial peripherals:
Two USART interfaces with pin functions assigned through the switch matrix and
one fractional baud rate generators.
One SPI controllers with pin functions assigned through the switch matrix.
Two I
2
C-bus interface. It supports data rates up to 400 kbit/s on standard digital
pins.
Clock generation:
Free Running Oscillator (FRO). This oscillator provides a selectable
9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO
is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C
to 70 C.
1 MHz low power oscillator can be used as a clock source.
Clock output function with divider that can reflect all internal clock sources.
Power control:
Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and
deep power-down mode.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
LPC804
Product data sheet
Rev. 1.4 — 12 July 2018
2 of 87
NXP Semiconductors
LPC804
32-bit Arm Cortex-M0+ microcontroller
Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and
I
2
C peripherals.
Wake-up from deep power-down mode on multiple pins.
Timer-controlled self wake-up from sleep, deep-sleep, and power-down modes.
Power-On Reset (POR).
Brownout detect (BOD).
Unique device serial number for identification.
Single power supply (1.71 V to 3.6 V).
Operating temperature range -40 °C to +105 °C.
Available in WLCSP20, TSSOP20, TSSOP24, and HVQFN33 packages.
LPC804
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.4 — 12 July 2018
3 of 87
NXP Semiconductors
LPC804
32-bit Arm Cortex-M0+ microcontroller
3. Applications
Sensor gateways
Industrial
Gaming controllers
8/16-bit applications
Consumer
Climate control
Simple motor control
Portables and wearables
Lighting
Motor control
Fire and security applications
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC804M101JDH20
LPC804M101JDH24
LPC804M111JDH24
LPC804M101JHI33
LPC804UK
TSSOP20
TSSOP24
TSSOP24
HVQFN33
WLCSP20
Description
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
Version
SOT360-1
SOT355-1
SOT355-1
Type number
HVQFN: plastic thermal enhanced very thin quad flat package; no leads; SOT617-11
33 terminals; body 5
5
0.85 mm
wafer level chip-size package; 20 (5
4) bumps; 2.50
1.84
0.5 mm
SOT1397-8
4.1 Ordering options
Table 2.
Ordering options
Dual I/O power supply
Type number
Capacitive Touch
SRAM/KB
Flash/KB
LPC804M101JDH20
LPC804M101JDH24
LPC804M111JDH24
LPC804M101JHI33
LPC804UK
32
32
32
32
32
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
-
1
1
1
-
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
17
21
20
30
17
-
-
yes
-
-
LPC804
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.4 — 12 July 2018
Package
TSSOP20
TSSOP24
TSSOP24
HVQFN33
WLCSP20
USART
GPIO
DAC
PLU
SPI
I
2
C
4 of 87
NXP Semiconductors
LPC804
32-bit Arm Cortex-M0+ microcontroller
5. Marking
20
Terminal 1 index area
NXP
Terminal 1 index area
1
aaa-014766
aaa-014382
Fig 1.
TSSOP20 and TSSOP24 package markings
Fig 2.
HVQFN33 package marking
Terminal 1
index area
aaa-015675
Fig 3.
WLCSP20 package marking
The LPC804 HVQFN33 packages have the following top-side marking::
•
First line: LPC804M1
•
Second line: xxxx
•
Third line: yywwx[R]
–
yyww: Date code with yy = year and ww = week.
–
xR = Boot code version and device revision.
The LPC804 TSSOP20 packages typically have the following top-side marking:
•
•
•
•
First line: LPC804
Second line: M101
Third line: xxxx
Fourth line: xxywwx[R]
–
yww: Date code with y = year and ww = week.
–
xR = Boot code version and device revision.
The LPC804 TSSOP24 packages have the following top-side marking:
LPC804
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.4 — 12 July 2018
NXP
5 of 87
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