LH540203D15 datasheet, PDF - EEWORLD Datasheet

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LH540203D15: DescriptionCMOS 2048X9 ASYNCHRONOUS FIFO; Categorystorage storage; File Size151KB，17 Pages; ManufacturerSHARP; Websitehttp://sharp-world.com/products/device/

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LH540203D15 Overview

CMOS 2048X9 ASYNCHRONOUS FIFO

LH540203D15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SHARP
package instruction	0.300 INCH, PLASTIC, DIP-28
Reach Compliance Code	unknow
period time	25 ns
JESD-30 code	R-PDIP-T28
JESD-609 code	e0
length	34.67 mm
memory density	18432 bi
memory width	9
Number of functions	1
Number of terminals	28
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX9
Exportable	NO
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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LH540203

FEATURES

•

Fast Access Times: 15/20/25/35/50 ns

•

Fast-Fall-Through Time Architecture Based on

CMOS Dual-Port SRAM Technology

•

Input Port and Output Port Have Entirely

Independent Timing

•

Expandable in Width and Depth

•

Full, Half-Full, and Empty Status Flags

•

Data Retransmission Capability

•

TTL-Compatible I/O

•

Pin and Functionally Compatible with Sharp LH5498

and with Am/IDT/MS7203

•

Control Signals Assertive-LOW for Noise Immunity

•

Packages:

28-Pin, 300-mil PDIP

28-Pin, 300-mil SOJ *

32-Pin PLCC

CMOS 2048

9 Asynchronous FIFO

FUNCTIONAL DESCRIPTION

The LH540203 is a FIFO (First-In, First-Out) memory

device, based on fully-static CMOS dual-port SRAM tech-

nology, capable of storing up to 2048 nine-bit words. It

follows the industry-standard architecture and package

pinouts for nine-bit asynchronous FIFOs. Each nine-bit

LH540203 word may consist of a standard eight-bit byte,

together with a parity bit or a block-marking/framing bit.

The input and output ports operate entirely inde-

pendently of each other, unless the LH540203 becomes

either totally full or else totally empty. Data flow at a port

is initiated by asserting either of two asynchronous, as-

sertive-LOW control inputs: Write (W) for data entry at the

input port, or Read (R) for data retrieval at the output port.

Full, Half-Full, and Empty status flags monitor the

extent to which the internal memory has been filled. The

system may make use of these status outputs to avoid

the risk of data loss, which otherwise might occur either

by attempting to write additional words into an already-full

LH540203, or by attempting to read additional words from

an already-empty LH540203. When an LH540203 is

operating in a depth-cascaded configuration, the Half-Full

Flag is not available.

PIN CONNECTIONS

28-PIN PDIP

28-PIN SOJ

FL/RT

XO/HF

540203-2D

32 31 30

FL/RT

XO/HF

14 15 16 17 18 19 20

NOTE:

= No external electrical connections are allowed.

540203-3D

Figure 1. Pin Connections for PDIP and

SOJ * Packages

Figure 2. Pin Connections for PLCC Package

* This is a final data sheet; except that all references to the SOJ package have Advance Information status.

TOP VIEW

32-PIN PLCC

TOP VIEW

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