530JB100M000DG datasheet, PDF - EEWORLD Datasheet

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530JB100M000DG: DescriptionStandard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS); CategoryPassive components; File Size1MB，12 Pages; ManufacturerSilicon Laboratories

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530JB100M000DG Overview

Standard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS)

530JB100M000DG Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Standard Clock Oscillators
Frequency	100 MHz
Frequency Stability	31.5 PPM
Load Capacitance	15 pF
Operating Supply Voltage	1.8 V
Supply Voltage - Min	1.71 V
Supply Voltage - Max	1.89 V
Output Format	CMOS
Termination Style	SMD/SMT
Package / Case	5 mm x 7 mm
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Length	7 mm
Width	5 mm
Height	1.65 mm
Packaging	Tray
Current Rating	81 mA
Type	Crystal Oscillator
Duty Cycle - Max	55 %
Mounting Style	SMD/SMT

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S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Z T O

1 . 4 GH

)

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications



SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

GND

CLK+

Si530 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

CLK–

GND

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.4 5/13

Si530/531

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