SN74LS194A
4-Bit Bidirectional
Universal Shift Register
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal
Shift Register. As a high speed multifunctional sequential building
block, it is useful in a wide variety of applications. It may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and
parallel-parallel data register transfers. The LS194A is similar in
operation to the LS195A Universal Shift Register, with added features
of shift left without external connections and hold (do nothing) modes
of operation. It utilizes the Schottky diode clamped process to achieve
high speeds and is fully compatible with all ON Semiconductor TTL
families.
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LOW
POWER
SCHOTTKY
•
•
•
•
•
Typical Shift Frequency of 36 MHz
Asynchronous Master Reset
Hold (Do Nothing) Mode
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
16
1
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
–0.4
8.0
Unit
V
°C
mA
mA
16
PLASTIC
N SUFFIX
CASE 648
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS194AN
SN74LS194AD
SN74LS194ADR2
Package
16 Pin DIP
SOIC–16
SOIC–16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 2001
1
October, 2001 – Rev. 7
Publication Order Number:
SN74LS194A/D
SN74LS194A
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
Q0
15
Q1
14
Q2
13
Q3
12
CP
11
S1
10
S0
9
1
MR
2
DSR
3
P0
4
P1
5
P2
6
P3
7
8
DSL GND
LOADING
(Note a)
PIN NAMES
S0, S1
P0 - P3
DSR
DSL
CP
MR
Q0 - Q3
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
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2
SN74LS194A
LOGIC DIAGRAM
10
P0
S1
S0
3
P1
4
P2
5
P3
6
9
DSR
2
7
DSL
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
S
CP
Q0
S
CP
Q1
S
CP
Q2
S
CP
Q3
R
CLEAR
R
CLEAR
R
CLEAR
R
CLEAR
CP
MR
11
1
15
14
13
12
Q0
Q1
Q2
Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing
on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2,
and Q3 outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW.
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S0, S1) determine the
synchronous operation of the device. As shown in the Mode
Selection Table, data can be entered and shifted from left to
right (shift right, Q0
!
Q1, etc.) or right to left (shift left, Q3
!
Q2, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S0 and S1,are
LOW, the existing data is retained in a “do nothing” mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
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3
SN74LS194A
MODE SELECT — TRUTH TABLE
INPUTS
OPERATING MODE
Reset
Hold
Shift Left
Shift Right
Parallel Load
MR
L
H
H
H
H
H
H
S1
X
I
h
h
I
I
h
S0
X
I
I
I
h
h
h
DSR
X
X
X
X
I
h
X
DSL
X
X
I
h
X
X
X
Pn
X
X
X
X
X
X
Pn
Q0
L
q0
q1
q1
L
H
P0
Q1
L
q1
q2
q2
q0
q0
P1
OUTPUTS
Q2
L
q2
q3
q3
q1
q1
P2
Q3
L
q3
L
H
q2
q2
P3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
–0.65
3.5
0.25
VOL
Output LOW Voltage
0.35
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
–20
–0.4
–100
0.5
20
IIH
IIL
IOS
V
µA
mA
mA
mA
0.4
Min
2.0
0.8
–1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = –18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
ICC
Power Supply Current
23
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
fMAX
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Propagation Delay,
MR to Output
Min
25
Typ
36
14
17
19
22
26
30
Max
Unit
MHz
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
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4
SN74LS194A
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
tW
ts
ts
th
trec
Parameter
Clock or MR Pulse Width
Mode Control Setup Time
Data Setup Time
Hold time, Any Input
Recovery Time
Min
20
30
20
0
25
Typ
Max
Unit
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
S0
1.3 V
tW
1.3 V
tPLH
1.3 V
S1
DSR DSL
P0 P1 P2 P3
th(L) = 0
CLOCK
OUTPUT*
1.3 V
ts(L)
th(L) = 0
ts(L)
1.3 V
ts(H)
th(H) = 0
ts(H)
th(H) = 0
1/fmax
CLOCK
OUTPUT
tPHL
1.3 V
(--- IS SHIFT LEFT)
OTHER CONDITIONS: S1 = L, MR = H, S0 = H
Figure 1. Clock to Output Delays Clock Pulse
Width and fmax
1.3 V
MR
1.3 V
tW
trec
1.3 V
tPHL
OTHER CONDITIONS: MR = H
OTHER CONDITIONS:
*DSR SET UP TIME AFFECTS Q0 ONLY
OTHER CONDITIONS:
DSL SET UP TIME AFFECTS Q3 ONLY
CLOCK
OUTPUT
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
1.3 V
S0 S1
ts
th = 0
(STABLE TIME)
1.3 V
th = 0
ts
1.3 V
OTHER CONDITIONS: S0, S1 = H
OTHER CONDITIONS:
PO = P1 = P2 = P3 = H
CLOCK
1.3 V
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
OTHER CONDITIONS: MR = H
Figure 4. Setup (ts) and Hold (th) Time for S Input
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