DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD160040B
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256-GRAY SCALE)
DESCRIPTION
The
µ
PD160040B is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scale. Data input
is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216
colors by output of 256 values
γ
-corrected by an internal D/A converter and 8-by-2 external power modules.
Because the output dynamic range is as large as V
SS2
+ 0.2 V to V
DD2
– 0.2 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray-scale voltage of differing polarity.
FEATURES
•
CMOS level input
•
384 outputs
•
Input of 8 bits (gray scale data) by 6 dots
•
Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
•
Logic power supply voltage (V
DD1
): 2.5 to 3.6 V
•
Driver power supply voltage (V
DD2
): 12.5 to 15.5 V (switchable, V
SEL
)
•
Output dynamic range: V
SS2
+ 0.2 V to V
DD2
– 0.2 V
•
High-speed data transfer: f
CLK.
= 55 MHz MAX. (internal data transfer speed when operating at 3.0 V
≤
V
DD1
≤
3.6 V)
f
CLK.
= 40 MHz MAX. (internal data transfer speed when operating at 2.5 V
≤
V
DD1
< 3.0 V)
•
Apply for dot-line inversion, n-line inversion and column line inversion
•
Output voltage polarity inversion function (POL)
•
Output inversion function (POL21, POL 22)
•
Output reset control is possible (MODE)
•
Trough-rate control is possible (SRC)
•
Output resistance control is possible (ORC)
•
Single bank arrangement is possible (Loaded with slim TCP)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD160040BN-xxx
Remark
The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15953EJ2V0DS00 (2nd edition)
Date Published January 2003 NS CP (K)
Printed in Japan
The mark
5
shows major revised points.
2001
µ
PD160040B
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
MODE
64-bit bidirectional shift register
C
1
C
2
C
63
C
64
STHL
V
DD1
V
SS1
D
00
-D
07
D
10
-D
17
D
20
-D
27
D
30
-D
37
D
40
-D
47
D
50
-D
57
POL21
POL22
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
D/A converter
V
0
-V
15
V
SEL
SRC
ORC
Voltage follower output
Input
TEST
S
1
S
2
S
3
S
384
Remark
/xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
383
S
384
V
7
V
8
V
15
·····
V
0
Multi-
plexer
8
8-bit D/A converter
8
·····
POL
2
Data Sheet S15953EJ2V0DS
µ
PD160040B
3. PIN CONFIGURATION (
µ
PD160040BN-xxx) (Copper Foil Surface, Face-up)
STHL
D
57
D
56
:
D
51
D
50
D
47
D
46
:
D
41
D
40
D
37
D
36
:
D
31
D
30
SRC
ORC
V
SEL
V
DD1
R,/L
V
15
V
14
V
13
V
12
V
11
V
10
V
9
V
8
V
DD2
V
SS2
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
V
SS1
MODE
TEST
CLK
STB
POL
POL22
POL21
D
27
D
26
:
D
21
D
20
D
17
D
16
:
D
11
D
10
D
07
D
06
:
D
01
D
00
STHR
S
384
S
383
S
382
Copper Foil
Surface
S
3
S
2
S
1
Remark
This figure does not specify the TCP package.
Data Sheet S15953EJ2V0DS
3
µ
PD160040B
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S
1
to S
384
D
00
to D
07
D
10
to D
17
D
20
to D
27
D
30
to D
37
D
40
to D
47
D
50
to D
57
R,/L
Shift direction control
Input
The shift direction control pin of shift register. The shift directions of the
shift registers are as follows.
R,/L = H (right shift): STHR (input)
→S
1
→S
384
→STHL
(output)
R,/L = L (left shift) : STHL (input)
→S
384
→S
1
→STHR
(output)
Port 2 display data
Input
Driver
Port 1 display data
Pin Name
I/O
Output
Input
Description
The D/A converted 256-gray-scale analog voltage is output.
The display data is input with a width of 48 bits, viz., the gray scale data
(8 bits) by 6 dots (2 pixels).
D
X0
: LSB, D
X7
: MSB
5
STHR
Right shift start pulse
I/O
These are the start pulse input/output pins when connected in cascade.
Loading of display data starts when a H level is read at the rising edge
of CLK.
A H level should be input at the pulse of one cycle of the clock signal.
5
STHL
Left shift start pulse
I/O
If the start pulse input is more than 2 CLK, the first 1 CLK of the H-level
input is valid.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
CLK
Shift clock
Input
The shift clock input pin of shift register. The display data is loaded into
the data register at the rising edge.
When 66 clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
STB
Latch
Input
The contents of the data register are transferred to the latch circuit at
the rising edge. In addition, at the falling edge, the gray scale voltage is
supplied to the driver. It is necessary to ensure input of one pulse per
horizontal period.
SRC
Through rate control
Input
SRC = H: High through rate mode (large current consumption)
SRC = L: Low through rate mode (small current consumption)
SRC is pulled up to the V
DD1
in the IC.
ORC
Output resistance control
Input
ORC = H: Low output resistance mode
ORC = L: High output resistance mode
ORC is pulled up to the V
DD1
in the IC.
POL
Polarity input
Input
POL = L: The S
2n−1
output uses V
0
-V
7
as the reference supply. The S
2n
output uses V
8
-V
15
as the reference supply.
POL = H: The S
2n−1
output uses V
8
-V
15
as the reference supply. The S
2n
output uses V
0
-V
7
as the reference supply.
S
2n−1
indicates the odd output and S
2n
indicates the even output. Input
of the POL signal is allowed the setup time (t
POL–STB
) with respect to
STB’s rising edge.
When it switches such as POL = H→L or L→H, all output pins are
output reset during STB = H. When it does not switch, all output pins
become Hi-Z (high impedance) during STB = H. Refer to
7.
RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND
OUTPUT WAVEFORM
for details.
4
Data Sheet S15953EJ2V0DS
µ
PD160040B
(2/2)
Pin Symbol
MODE
Pin Name
Output reset control
I/O
Input
MODE = L: No output reset
MODE is pulled up to the V
DD1
in the IC.
POL21,
POL22
Data inversion
Input
Select of inversion or no inversion for input data.
POL21: Data inversion or no inversion of Port1.
POL22: Data inversion or no inversion of Port2
POL21, POL22 = H: Data are inverted in the IC.
POL21, POL22 = L: Data are not inverted in the IC.
V
SEL
Driver voltage select
Input
The driver voltage can be switched by controlling the stationary bias
current of the output amplifier via V
SEL
.
V
SEL
= H: V
DD2
= 12.5 to (14.0 V) (large bias current)
V
SEL
= L or open: V
DD2
= (14.0 V) to 15.5 V (small bias current)
LPC is pulled down to the V
SS1
in the IC.
V
0
-V
15
Description
MODE = H or open: Output reset
γ
-corrected power supplies
−
Input the
γ
-corrected power supplies from outside by using operational
amplifier. During the gray scale voltage output, be sure to keep the gray
scale level power supply at a constant level. Make sure to maintain the
following relationships.
V
DD2
– 0.2 V
≥
V
0
> V
1
> V
2
> ... ..., > V
6
> V
7
≥
0.5 V
DD2
+ 0.5 V
0.5 V
DD2
– 0.5 V
≥
V
8
> V
9
> V
10
> ... ..., > V
14
> V
15
≥
0.5 V
SS2
+ 0.2 V
TEST
V
DD1
V
DD2
V
SS1
V
SS2
Test
Logic power supply
Driver power supply
Logic ground
Driver ground
Input
−
−
−
−
Normally, set the TEST pin to H level or leave open.
This pin is pulled up to V
DD1
in the IC.
2.5 to 3.6 V
12.5 to 15.5 V
Grounding
Grounding
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
-V
15
in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.47
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
.
Furthermore, for increased precision of the D/A converter,
insertion of a bypass capacitor of about 0.1
µ
F is also advised between the
γ
-corrected
power supply terminals (V
0
, V
1
, V
2
,....., V
15
) and V
SS2
.
Data Sheet S15953EJ2V0DS
5
京公网安备 11010802033920号
EEWORLD
