CD74HC32M96G4 datasheet, PDF - EEWORLD Datasheet

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CD74HC32M96G4: DescriptionLogic Gates Hi Sp CMOS Log Quad 2-Input OR; Categorylogic logic; File Size405KB，13 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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CD74HC32M96G4 Overview

Logic Gates Hi Sp CMOS Log Quad 2-Input OR

CD74HC32M96G4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	SOP, SOP14,.25
Contacts	14
Reach Compliance Code	unknow
series	HC/UH
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	OR GATE
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	2/6 V
Prop。Delay @ Nom-Su	27 ns
propagation delay (tpd)	135 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm

CD74HC32M96G4 Related Products

	CD74HC32M96G4	CD74HCT32MTG4	CD74HCT32MTE4	CD74HCT32MT	CD74HCT32MG4	CD74HCT32M96E4	CD74HC32MTE4	CD74HC32M96E4
Description	Logic Gates Hi Sp CMOS Log Quad 2-Input OR	Logic Gates Hi Spd CMOS Log Quad Two-Input OR	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp OR Gate	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp OR Gate	Logic Gates Hi Spd CMOS Log Quad Two-Input OR	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp OR Gate	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp OR Gate	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp OR Gate
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	SOP, SOP14,.25	SOP, SOP14,.25	SOP, SOP14,.25	SOP, SOP14,.25	GREEN, PLASTIC, MS-012AB, SOIC-14	GREEN, PLASTIC, MS-012AB, SOIC-14	SOP, SOP14,.25	SOP, SOP14,.25
Contacts	14	14	14	14	14	14	14	14
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow	unknow	unknow	unknow
series	HC/UH	HCT	HCT	HCT	HCT	HCT	HC/UH	HC/UH
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4	e4	e4	e4	e4
length	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE	OR GATE
MaximumI(ol)	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
Humidity sensitivity level	1	1	1	1	1	1	1	1
Number of functions	4	4	4	4	4	4	4	4
Number of entries	2	2	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP	SOP	SOP	SOP	SOP
Encapsulate equivalent code	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
method of packing	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TUBE	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260	260
power supply	2/6 V	5 V	5 V	5 V	5 V	5 V	2/6 V	2/6 V
Prop。Delay @ Nom-Su	27 ns	36 ns	36 ns	36 ns	36 ns	36 ns	27 ns	27 ns
propagation delay (tpd)	135 ns	36 ns	36 ns	36 ns	36 ns	36 ns	135 ns	135 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO	NO
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	6 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	6 V	6 V
Minimum supply voltage (Vsup)	2 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm

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