NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from
90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz
low-pass filter and 400Hz high-pass filter.
®
PCM1760P/U DF1760P/U
2
ABSOLUTE MAXIMUM RATINGS—PCM1760
Supply Voltage .....................................................................................
±6V
Voltage Mismatch ............................................................................... 0.1V
Analog Input ........................................................................................
±V
CC
Digital Input ............................................................................... +V
DD
+0.3V
GND –0.3V
Power Dissipation/P ....................................................................... 580mW
Power Dissipation/U ....................................................................... 550mW
Lead Temperature/P (soldering, 10s) .............................................. 260°C
Lead Temperature/U (soldering, 10s) .............................................. 235°C
Operating Temperature ......................................................... 0°C to +70°C
Storage Temperature ...................................................... –50°C to +125°C
ABSOLUTE MAXIMUM RATINGS—DF1760
Supply Voltage .................................................................................... 7.0V
Voltage Mismatch ............................................................................... 0.1V
Digital Input ............................................................................... +V
DD
+0.5V
V
SS
–0.5V
Input Current
±20mA
Power Dissipation/P ....................................................................... 460mW
Power Dissipation/U ....................................................................... 440mW
Lead Temperature/P (soldering, 10s) .............................................. 260°C
Lead Temperature/U (soldering, 10s, reflow) ................................... 235°C
Operating Temperature .......................................................... 0°C to +70°c
Storage Temperature ...................................................... –50°C to +125°C
ORDERING INFORMATION
MODEL
PCM1760P
PCM1760U
PCM1760P-L
PCM1760U-L
DF1760P
DF1760U
PACKAGE
PDIP
SOIC
PDIP
SOIC
PDIP
SOIC
THD +N (fs)
–90dB
–90dB
–88dB
–88dB
NA
NA
SNR
108dB
108dB
106dB
106dB
NA
NA
PACKAGE INFORMATION
MODEL
PCM1760P
PCM1760U
PCM1760P-L
PCM1760U-L
DF1760P
DF1760U
PACKAGE
28-Pin PDIP
28-Pin SOIC
28-Pin PDIP
28-Pin SOIC
28-Pin PDIP
28-Pin SOIC
PACKAGE DRAWING
NUMBER
(1)
800
804
800
804
801
805
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
PIN ASSIGNMENTS PCM1760
Top View
SOIC/DIP
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
(1)
O
I
O
I
–
–
–
–
–
–
I
O
I
O
–
–
O
O
I
–
–
–
O
O
O
O
–
–
NAME
Out-2R
In-2R
Out-1R
In-1R
SERVO DC
+V
CC
AGND
–V
CC
BGDC
NC
In-1L
Out-1L
In-2L
Out-2L
NC
BPODC-L
L/RCK
Strobe
256fs
–V
DD
DGND
+V
DD
D
0
D
1
D
2
D
3
BPODC-R
NC
DESCRIPTION
Right Channel Second Integrator Output
Right Channel Second Integrator Input
Right Channel First Integrator Output
Right Channel First Integrator Input
Servo Amp Decoupling Capacitor
+5V Analog Supply Voltage
Analog Common
–5V Analog Supply Voltage
Band Gap Reference Decoupling Capacitor
No Connection
Left Channel First Integrator Input
Left Channel First Integrator Output
Left Channel Second Integrator Input
Left Channel Second Integrator Output
No Connection
Left Channel Bipolar Offset Decoupling Capacitor
LR Clock Output (64fs)
Data Strobe Output (128fs)
256fs Clock Input
–5V Digital Supply Voltage
Digital Common
+5V Digital Supply Voltage
D
0
Data Output (LSB)
D
1
Data Output
D
2
Data Output
D
3
Data Output (MSB)
Right Channel Bipolar Offset Decoupling Capacitor
No Connection
Out-2R
In-2R
Out-1R
In-1R
SERVO DC
+V
CC
AGND
–V
CC
BGDC
1
2
3
4
5
6
7
PCM1760
8
9
28 NC
27 BPODC-R
26 D
3
25 D
2
24 D
1
23 D
0
22 +V
DD
21 DGND
20 –V
DD
19 256fs
18 Strobe
17 L/RCK
16 BPODC-L
15 NC
NC 10
In-1L 11
Out-1L 12
In-2L 13
Out-2L 14
NOTE: (1) O = Output terminal; I = Input terminal.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
PCM1760P/U DF1760P/U
PIN ASSIGNMENTS DF1760
Top View
OVL
OVR
D
3
D
2
D
1
D
0
TP1
V
SS1
V
DD1
1
2
3
4
5
6
7
DF1760
8
9
21 /PD
20 LRSC
19 FSYNC
18 SDATA
17 L/R
16 SCLK
15 SYSCLK
28 V
SS2
27 V
DD2
26 TP2
25 CLKSEL
24 S/M
23 Mode 1
22 Mode 2
SOIC/DIP
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
(1)
O
O
I
I
I
I
–
–
–
O
I
I
I↑
O
I
I↑ /O
I↑ /O
O
I↑ /O
I↑
I↑
I↑
I↑
I↑
I↑
–
–
–
NAME
OVL
OVR
D
3
D
2
D
1
D
0
TP1
V
SS1
V
DD1
256fs
Strobe
LRCK
CALD
CAL
SYSCLK
SCLK
L/R
SDATA
FSYNC
LRSC
/PD
Mode2
Mode1
S/M
CLKSEL
TP2
V
DD2
V
SS2
DESCRIPTION
Left Channel Overflow Output (Active High)
Right Channel Overflow Output (Active High)
D3 Data Input (MSB)
D2 Data Input
D1 Data Input
D0 Data Input (LSB)
Test Pin (No Connection)
Common Channel 1
+5V Channel 1
256fs Clock Output
Data Strobe Clock Input (128fs)
LR Clock Input
Calibration Function Enable (Active Low)
Calibration Output (High During Calibration)
System Clock Input (256fs or 384fs)
Data Clock
LR Channel Phase Clock
Serial Data Output (1fs)
Frame Clock (2fs)
Phase Control of LR Channel Phase Clock
Power Down Mode Enable Input (Active Low)
Output Format Selection Input 2
Output Format Selection Input 1
Slave/Master Mode Selection Input (High Makes
Slave Mode
System Clock Selection Input (High Makes 256fs)
Test Pin (No Connection)
+5V Channel 2
Common Channel 2
256fs 10
Strobe 11
LRCK 12
CALD 13
CAL 14
NOTE: (1) O = Output terminal; I = Input terminal.
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