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531AB622M080DGR

Description
Standard Clock Oscillators Single Frequency XO, OE Pin 1
CategoryPassive components   
File Size1MB,12 Pages
ManufacturerSilicon Laboratories
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531AB622M080DGR Overview

Standard Clock Oscillators Single Frequency XO, OE Pin 1

531AB622M080DGR Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerSilicon Laboratories
Product CategoryStandard Clock Oscillators
Frequency622.08 MHz
Frequency Stability31.5 PPM
Load Capacitance15 pF
Operating Supply Voltage3.3 V
Supply Voltage - Min2.97 V
Supply Voltage - Max3.63 V
Output FormatLVPECL
Termination StyleSMD/SMT
Package / Case5 mm x 7 mm
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Length7 mm
Width5 mm
Height1.65 mm
PackagingBox
Current Rating111 mA
TypeCrystal Oscillator
Duty Cycle - Max55 %
S i 5 3 0 / 5 31
R
EVISION
D
C
R YS TA L
O
SCILLATOR
(XO) (10 M H
Z T O
1 . 4 GH
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
OE
2
5
CLK–
GND
3
4
CLK+
Si530 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
2
5
NC
GND
3
4
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
1
6
V
DD
NC
2
5
CLK–
GND
3
4
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.4 5/13
Copyright © 2013 by Silicon Laboratories
Si530/531
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Index Files: 206  311  2876  2813  2411  5  7  58  57  49 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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