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SI5344H-D06933-GM

Description
Clock Synthesizer / Jitter Cleaner 100G/400G Coherent Optics Clock, 2-Output, <2.7GHz, Jitter Attenuator, DCO
Categorysemiconductor    Analog mixed-signal IC   
File Size1MB,56 Pages
ManufacturerSilicon Laboratories
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SI5344H-D06933-GM Overview

Clock Synthesizer / Jitter Cleaner 100G/400G Coherent Optics Clock, 2-Output, <2.7GHz, Jitter Attenuator, DCO

SI5344H-D06933-GM Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerSilicon Laboratories
Product CategoryClock Synthesizer / Jitter Cleaner
Si5344H/42H Rev D
H
I G H
-F
R E Q U E N C Y
, U
LTRA
-L
O W
J
I T T E R
A
T T E N U A T O R
C
L O C K
W I T H
D
IG ITA LLY
- C
O N T R O L L E D
O
S C I L L A T O R
Features
High-speed outputs generate an
ultra-low jitter output up to 2.75 GHz
Up to four Multi-Synth outputs
generate any frequency up to
717.5 MHz
Input frequency range:

8 kHz to 750 MHz
Maximum Output frequency:

High-Frequency Mode: 2.75 GHz

MultiSynth Mode: 717.5 MHz
Jitter performance:
High Frequency Mode:
<50 fs typ (1 MHz–40 MHz)
MultiSynth Mode:
<150 fs typ (12 kHz–20 MHz)
Programmable jitter attenuation
bandwidth: 10 Hz to 4 kHz
Highly configurable outputs
compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with
programmable voltage swing and
common mode

LVPECL-only in High Frequency
Mode
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching:
automatic or manual
Automatic free-run and holdover
modes
Glitchless on the fly output
frequency changes
Locks to gapped clock inputs
DCO mode: as low as 0.001 ppb
steps.
Core voltage

V
DD
: 1.8 V ±5%

V
DDA
:
3.3 V ±5%
Independent output supply pins:
3.3 V, 2.5 V, or 1.8 V
Serial interface: I
2
C or SPI
In-circuit programmable with
non-volatile OTP memory
ClockBuilder Pro
TM
software
simplifies device configuration
Si5342H: 2 input, 2 output, QFN44
Si5344H, 2 input, 4 output, QFN44
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Ordering Information:
See Section 7.
Pin Assignments
Si5342H 44QFN
Top View
I2C_SEL
RSVD_GND
VDDS
34
NC
VDD
IN0
IN0
NC
VDD
NC
36
44
43
42
41
40
39
38
37
IN1
IN1
IN_SEL0
X1
XA
XB
X2
VDDA
35
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
INTR
VDD
LOS1
LOS0
VDDS
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
Applications
GND
Pad
29
28
27
26
25
24
23
100G/200G/400G Optical
Transceivers
Wireless base-stations
VDDA
NC
NC
OUT0
VDD
OE
SDA/SDIO
A1/SDO
A0/CS
RST
OE
SDA/SDIO
A1/SDO
A0/CS
Rev. 1.0 9/16
Copyright © 2016 by Silicon Laboratories
VDDO0
OUT0
SCLK
OUT0
VDD
RST
NC
This specialized jitter attenuating clock multiplier combines fourth-generation
DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high
data rate coherent optical transceiver design. Up to four outputs can be assigned
to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase
jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode
any-frequency outputs when added frequency flexibility is required, such as
clocking Forward Error Correction (FEC) while still delivering <150 fs-rms typical
phase jitter (12 kHz-20 MHz). The Si5344H and Si5342H also feature DCO-
control with as low as 0.001 ppb step control and locks to gapped clock inputs.
These devices are programmable via a serial interface with in-circuit
programmable non-volatile memory (NVM) so that they always power up with a
known frequency configuration. The loop filter is fully integrated on-chip
eliminating the risk of potential noise coupling associated with discrete solutions.
Programming the Si5342H/44H is made easy with Silicon Labs’
ClockBuilderPro
software. Factory preprogrammed devices are also available.
Si5344H 44QFN
Top View
I2C_SEL
IN_SEL1
VDDO3
34
VDDO0
OUT0
SCLK
Description
OUT3
36
44
43
42
41
40
39
38
37
IN1
IN1
IN_SEL0
XGND
XA
XB
XGND
VDDA
VDDA
NC
NC
35
OUT3
NC
VDD
IN0
IN0
NC
VDD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
INTR
VDD
OUT2
OUT2
VDDO2
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
GND
Pad
29
28
27
26
25
24
23
Si5344H/42H
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